XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 348

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7: SelectIO Logic Resources
348
ODDR VHDL and Verilog Templates
OLOGIC Timing Models
Timing Characteristics
The Libraries Guide includes templates for instantiation of the ODDR module in VHDL
and Verilog.
This section discusses all timing models associated with the OLOGIC block.
describes the function and control signals of the OLOGIC switching characteristics in the
Virtex-5 FPGA Data Sheet.
Table 7-15: OLOGIC Switching Characteristics
Figure 7-26
X-Ref Target - Figure 7-26
Setup/Hold
T
T
T
T
T
Clock to Out
T
T
OCE
CLK
ODCK
OOCECK
OSRCK
OTCK
OTCECK
OCKQ
RQ
OQ
SR
D1
/T
Symbol
/T
/T
/T
/T
OCKT
OCKD
OCKSR
illustrates the OLOGIC output register timing.
Figure 7-26: OLOGIC Output Register Timing Characteristics
OCKTCE
OCKOCE
1
T
T
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
CLK to OQ/TQ out
SR/REV pin to OQ/TQ out
ODCK
OOCECK
www.xilinx.com
T
OCKQ
2
Description
3
4
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T
OSRCK
Table 7-15
ug190_7_21_041206
5