XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 46

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1: Clock Resources
VHDL and Verilog Templates
46
Regional Clock Nets
In addition to global clock trees and nets, Virtex-5 devices contain regional clock nets.
These clock trees are also designed for low-skew and low-power operation. Unused
branches are disconnected. The clock trees also manage the load/fanout when all the logic
resources are used.
Regional clock nets do not propagate throughout the whole Virtex-5 device. Instead, they
are limited to only one clock region. One clock region contains four independent regional
clock nets.
To access regional clock nets, BUFRs must be instantiated. A BUFR can drive regional
clocks in up to two adjacent clock regions
can only access one adjacent region; below or above respectively. The left side BUFRs can
feed the center column I/Os.
X-Ref Target - Figure 1-23
The VHDL and Verilog code for all clocking resource primitives and ISE language
templates are available in the Libraries Guide.
BUFRs
Figure 1-23: BUFR Driving Multiple Regions
www.xilinx.com
(Figure
1-23). BUFRs in the top or bottom region
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_23_012306