XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 186

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5: Configurable Logic Blocks (CLBs)
186
X-Ref Target - Figure 5-11
Implementation of distributed RAM configurations with depth greater than 64 requires the
usage of wide-function multiplexers (F7AMUX, F7BMUX, and F8MUX).
WADDR[6:1]
RADDR[6:1]
DATA[2]
DATA[1]
DATA[3]
unused
unused
WCLK
WED
Figure 5-11: Distributed RAM (RAM64X3SDP)
www.xilinx.com
D[6:1]
C[6:1]
A[6:1]
B[6:1]
RAM 64X3SDP
(CLK)
(WE)
6
6
6
6
6
6
6
6
DI1
DI2
A[6:1]
WA[6:1]
CLK
WE
DI1
DI2
A[6:1]
WA[6:1]
CLK
WE
DI1
DI2
A[6:1]
WA[6:1]
CLK
WE
DI1
DI2
A[6:1]
WA[6:1]
CLK
WE
DPRAM32
DPRAM32
DPRAM32
DPRAM32
O6
O5
O6
O5
O6
O5
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_5_06_050506
O[1]
O[2]
O[3]