XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 29

• Manufacturer Part Number: XC5VLX50-1FFG676I
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG676I

• Package: 676FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 440
• Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 1769472
• Number Of I /o: 440
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 676-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
BUFGCTRL is designed to switch between two clock inputs without the possibility of a
glitch. When the presently selected clock transitions from High to Low after S0 and S1
change, the output is kept Low until the other (to-be-selected) clock has transitioned from
High to Low. Then the new clock starts driving the output.The default configuration for
BUFGCTRL is falling edge sensitive and held at Low prior to the input switching.
BUFGCTRL can also be rising edge sensitive and held at High prior to the input switching.
In some applications the conditions previously described are not desirable. Asserting the
IGNORE pins will bypass the BUFGCTRL from detecting the conditions for switching
between two clock inputs. In other words, asserting IGNORE causes the mux to switch the
inputs at the instant the select pin changes. IGNORE0 causes the output to switch away
from the I0 input immediately when the select pin changes, while IGNORE1 causes the
output to switch away from the I1 input immediately when the select pin changes.
Selection of an input clock requires a “select” pair (S0 and CE0, or S1 and CE1) to be
asserted High. If either S or CE is not asserted High, the desired input will not be selected.
In normal operation, both S and CE pairs (all four select lines) are not expected to be
asserted High simultaneously. Typically only one pin of a “select” pair is used as a select
line, while the other pin is tied High. The truth table is shown in
Table 1-3: Truth Table for Clock Resources
Although both S and CE are used to select a desired output, each one of these pins behaves
slightly different. When using CE to switch clocks, the change in clock selection can be
faster than when using S. Violation in Setup/Hold time of the CE pins causes a glitch at the
clock output. On the other hand, using the S pins allows the user to switch between the two
clock inputs without regard to Setup/Hold times. It will not result in a glitch. See
BUFGMUX_CTRL. The CE pin is designed to allow backward compatibility from Virtex-II
and Virtex-II Pro FPGAs.
Notes:
1. Old input refers to the valid input clock before this state is achieved.
2. For all other states, the output becomes the value of INIT_OUT and does not toggle.
CE0
X
1
1
0
1
S0
www.xilinx.com
X
1
1
0
1
CE1
X
0
1
1
1
Global Clocking Resources
S1
X
0
1
1
1
Table
1-3.
Old Input
O
I0
I0
I1
I1
(1)
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