SCD128410QCE Intel, SCD128410QCE Datasheet - Page 108

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.0
7.1
7.1.1
7.1.2
108
Register Name: CAR
Register Description: Channel Access
Access: Read/Write
Register Name: GFRCR
Register Description: Global Firmware Revision Code
Access: Read/Write
Bit 7
Bit 7
Poll
Detailed Register Descriptions
This section presents a complete and detailed description of each register. Registers have two
formats: 1) full eight bits, where the entire content defines a single function; 2) the register is a
collection of bits, grouped singly or in multiples, defining a function. In the second format, the
descriptions divide the register into its component parts and describe the bits individually. The
order of register presentation corresponds to the register summary tables in
Global Registers
Channel Access Register
The CAR provides access to individual channels within the CD1284. The least-significant two bits
of the register select one of the four channels. Before any operation that affects a channel, this
register must be loaded so that channel registers are available to the host. Bit 2 must always be ‘0’.
Bits 7:3 are not used except during Poll-mode operation (see
Global Firmware Revision Code Register
The GFRCR serves two purposes in the CD1284. First, it displays the revision number of the
firmware in the chip. When a revision to the CD1284 is required, the revision number of the
firmware is incremented by one. The revision code is 24 (hex) for the Revision D device, and 25
(hex) for the Revision E device.
Bit 6
Bit 6
Poll
C1
0
0
1
1
Bit 5
Bit 5
Poll
C0
0
1
0
1
Firmware Revision Code
Bit 4
Bit 4
Poll
Channel 0
Not used
Channel 2
Channel 3
Bit 3
Channel Selected
Bit 3
Poll
Bit 2
Bit 2
Section 6.3
0
for details).
Bit 1
Bit 1
Chapter
C1
8-Bit Hex Address: 68
8-Bit Hex Address: 4F
Default Value: XX
Default Value: 25
4.0.
Datasheet
Bit 0
Bit 0
C0