SCD128410QCE Intel, SCD128410QCE Datasheet - Page 115

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

7.2.3
7.2.4
Datasheet
Register Name: PIVR
Register Description: Parallel Interrupt Vector
Access: Read only
Register Name: RDSR
Register Description: Receive Data
Access: Read only
Register Name: RDSR
Register Description: Receive Status
Access: Read only
Timeout
Bit 7
Bit 7
Bit 7
X
Parallel Interrupt Vector Register
The value in this register is placed on the data bus, DB[7:0], when SVCACKP* is activated in
response to an active SVCREQP*. See
Receive Data/Status Registers
The Receive Data/Status register serves two purposes. During a serial receive-service acknowledge
for good data, the RDSR provides access to the receive FIFO. The number of characters available
in the FIFO is indicated by the RDCR, and is described in
up to the value in the RDCR, can be read from the FIFO. All internal FIFO pointers are updated by
the on-chip processor.
During a serial receive exception service acknowledge, the RDSR provides both the received
character and the status that caused the exception condition. By definition, a receive exception
service request has only one character available (multiple receive exceptions produce multiple
service requests). The first read from the RDSR provides the exception status, and the second read
SC Det2
Bit 6
Bit 6
Bit 6
X
IT2
0
0
0
0
1
1
1
1
l
SC Det1
Bit 5
Bit 5
Bit 5
IT1
X
0
0
1
1
0
0
1
1
l
IEEE 1284-Compatible Parallel Interface Controller — CD1284
SC Det0
IT0
Bit 4
Bit 4
Bit 4
Received Character
0
1
0
1
0
1
0
1
l
X
Section 7.4.6 on page 128
No parallel interrupt source is active.
Group 1: Modem signal change service request.
Invalid.
The parallel port state machine requests service.
The parallel port data pipeline requests service.
Both the parallel port state machine and the parallel port data
pipeline request service.
Invalid.
Break
Bit 3
Bit 3
Bit 3
X
Section
Bit 2
Bit 2
Bit 2
IT2
PE
Description
for more details on the LIVR.
7.5. Any number of characters,
Bit 1
Bit 1
Bit 1
IT1
FE
8-Bit Hex Address: 40
8-Bit Hex Address: 62
8-Bit Hex Address: 62
Default Value: 00
Default Value: 00
Default Value: 00
Bit 0
Bit 0
Bit 0
IT0
OE
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