SCD128410QCE Intel, SCD128410QCE Datasheet - Page 129

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

7.4.7
7.5
7.5.1
Datasheet
Register Name: LNC
Register Description: LNext Character
Access: Read/Write
Register Name: MCOR1
Register Description: Modem Change Option Register 1
Access: Read/Write
DSRzd
Bit 7
Bit 7
LNext Character Register
This register defines the LNext character. If the LNext function is enabled (COR5[6]), the CD1284
examines received characters and compare them against this value. If a match occurs, this character
and the following are placed in the FIFO without any special processing. In effect, the LNext
function causes the CD1284 to ignore characters with special meaning, such as flow-control
characters. There are two exceptions. If the character following the LNext character is either a
break or an error character, LNext is placed in the FIFO, and the following character are treated as
it normally would be for these error conditions.
Modem Change Option Registers
The CD1284 has two registers that control its response to changes on the modem input pins. It can
be programmed to respond to the low-to-high transition, the high-to-low transition or both. In
addition, the threshold at which the DTR signal is negated can be set by the DTRth3–DTRth0 bits
in MCOR1.
Modem Change Option Register 1
CTSzd
Bit 6
Bit 6
Bit 5
Bit 5
RIzd
IEEE 1284-Compatible Parallel Interface Controller — CD1284
CDzd
Bit 4
Bit 4
LNext Character
DTRth3
Bit 3
Bit 3
DTRth2
Bit 2
Bit 2
DTRth1
Bit 1
Bit 1
8-Bit Hex Address: 24
8-Bit Hex Address: 15
Default Value: 00
Default Value: 00
DTRth0
Bit 0
Bit 0
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