SCD128410QCE Intel, SCD128410QCE Datasheet - Page 78

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
5.12.3
5.12.4
78
DB[15:8]
DB[7:0]
Table 20. Signal Names (Sheet 2 of 2)
Figure 11. FIFO Data Path Functional Diagram — Receive
State Machine
The parallel port is controlled by a large synchronous state machine. The state machine is based on
the IEEE STD 1284 specification and conforms to all the functional modes (except extensibility
link options, none of which are currently — as of the print date of this document — defined).
Configuration
At power-up, the interface begins in Compatibility mode (Centronics mode) ready to accept data
from the master. Only the ETxfr bit (PCR[5]) is required to allow transfers in Compatibility mode
(parallel port only; datapath section is separate). PCR[7:5] enable transfers and Negotiation and
Manual modes.
AkDaRq
PerBsy
PerClk
nDatAv
XFlag
Names
PError
BUSY
ACK*
FAULT*
SELECT
Compatibility
(RECEIVE)
TAG BIT
TAG BIT
PFSR
STATUS
TAG
Rev. NB
AkDaRq
nDatAv
PerBsy
PerClk
XFlag
STATUS
Outputs
TAG
Rev. BT
AkDaRq
PerBsy
nDatAv
PerClk
XFlag
FIFO (64 BYTES)
TAG (64 BITS)
nPerReq
nAkRev
PerAck
PerClk
XFlag
ECP
Datasheet
USER1
USER2
USER3
nWait
EPP
Intr