SCD128410QCE Intel, SCD128410QCE Datasheet - Page 140

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.7.7
7.7.8
140
Register Name: PCRR
Register Description: Parallel Channel Reset
Access: Read/Write
Register Name: PFCR
Register Description: Parallel FIFO Control
Access: Read/Write
FIFOres
Bit 7
Bit 7
0
Bit
Bit
7:1
2
1
0
0
Parallel Channel Reset Register
This register exists only in the Channel 0 register set and is in the equivalent address location as the
MSVR register of the serial channels.
Parallel FIFO Control Register
This register controls overall function of the parallel FIFO. These functions include resetting
(flushing) the FIFO, enabling DMA transfers, enabling host interrupts, run-length encoding, and so
on. The host sets these bits according to the mode of operation required.
After hard reset (RESET* or a CCR command of x’81 in one of the two serial channels), this
register is cleared to all zeros.
Reserved: Must be ‘0.’
AsyncDMA: AsyncDMA causes the device to synchronize the DMAACK* signal to the internal clock (rising
clock edge). This capability provides an asynchronous DMA interface for systems that cannot meet the set-up
times required by the synchronous DMA logic.
Refer to
enabled.
Unfair: This bit overrides the Fair Share function of the device. If this bit is set, the device posts service
requests even if the service request is already asserted by an external device. The override is in effect for
channels 2 and 3; Fair Share is not functional on the parallel service request.
For applications where the three serial channel service request outputs are wire-OR’ed together, set Unfair so
that an interrupt of one type does not prevent posting one of the other types (receive, transmit, and modem).
Reserved: Must be ‘0’
PChReset: Setting this bit asserts the equivalent of a hardware power-on reset to the parallel channel,
channel 0. If set by the host, it must be cleared to resume normal parallel channel operation. This hardware
reset affects only the parallel channel and has no affect on other functions of the device.
DMAen
Bit 6
Bit 6
0
Chapter 8.0
DMAdir
Bit 5
Bit 5
0
for specific timing relationships between CLK and DMAACK* when AsyncDMA is
IntEn
Bit 4
Bit 4
0
Description
Description
RLEen
Bit 3
Bit 3
0
setTAG
Bit 2
Bit 2
0
ErrEn
Bit 1
Bit 1
8-Bit Hex Address: 6C
8-Bit Hex Address: 31
0
Default Value: 00
Default Value: 00
DMAbufWe
Datasheet
PChReset
Bit 0
Bit 0