SCD128410QCE Intel, SCD128410QCE Datasheet - Page 124

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.4.2
124
Register Description: COR2
Register Description: Channel Option Register 2
Access: Read/Write
Bit 7
IXM
Bit
3:2
1:0
Bit
4
7
6
5
Channel Option Register 2
Ignore Parity: If this bit is set, the CD1284 ignores the parity on all incoming characters, thus no receive
exception service requests are generated if the parity is in error. If the bit is cleared, parity is evaluated.
Stop Bit Length: These two bits set the length, in bit times, of the Stop bit for each character.
Character Length: ChL1 and ChL0 select the length of each character, in number of bits. The CD1284
receives and transmits the same length character, on a given channel, in the range of five to eight bits.
Implied XON mode: This bit enables the automatic resumption of character transmission upon the reception
of any character. This bit only has meaning if the transmitter is in Automatic In-band Flow-control mode as
programmed by the TxIBE control bit. When this bit is reset and TxIBE is enabled, the reception of any
character restarts character transmission.
Enable Automatic In-band Transmit Flow Control: This bit allows the CD1284 to examine error-free
incoming characters looking for an XOFF character (as programmed by SCHR2), if the special character
match function is enabled (COR3[4]). If a match occurs, transmission ceases after the current characters in
the Transmitter Shift register and Transmitter Holding register are sent. Transmission resumes when an XON
character (or any character, depending on the value of the IXM bit) is received or if a channel enable
command is issued by the CCR.
Embedded Transmit Command Enable: If the ETC bit is set, the CD1284 examines characters in the
transmit FIFO. If an embedded command is detected, it is processed. See the embedded transmit command
description in
TxIBE
Bit 6
Stop1
ChL1
0
0
1
1
Chapter 5.0
0
0
1
1
Bit 5
ETC
for details of valid commands.
Stop0
ChL0
0
1
0
1
0
1
0
1
Bit 4
LLM
1
1.5
2
Not used.
5 bits
6 bits
7 bits
8 bits
Description
Description
Bit 3
RLM
Number of Stop Bits
Character Length
RtsAO
Bit 2
CtsAE
Bit 1
8-Bit Hex Address: 09
Default Value: 00
Datasheet
DsrAE
Bit 0