SCD128410QCE Intel, SCD128410QCE Datasheet - Page 77

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

5.12
5.12.1
5.12.2
Datasheet
Table 20. Signal Names (Sheet 1 of 2)
Another comparator determines if the next character coming from the DMABUF register and the
character in PFHR1 are identical. Compression begins when the pipeline is full (immediately after
a DMA or CPU write to the DMA buffer) and both comparators show identical characters in their
pipeline stages. This starts the compression process and the character in PFHR1 and the DMA
buffer shift forward. The (same) character in PFHR2 is not loaded into the FIFO, but rather the
RLCR increments to ‘1’.
As long as identical additional characters are loaded into the DMA buffer, the RLCR value
continues to increment and the data in PFHR2 does not move into the FIFO. When the repeated
sequence is finally broken, or the RLCR count reaches 127, the RLCR value transfers into the
FIFO, the RLCR zeros, and the character in PFHR2 transfers into the FIFO. Compression resumes
when both comparators indicate the presence of a string of at least three identical characters.
During intervals between DMA transfers, the last two data characters are held in PFHR1 and
PFHR2.
After the entire block transfer is complete, the CPU must either zero RLEen or ensure that both
DMAen and DMAbufWe are zeros. When either of these conditions is true, the pipeline is released
and data held in PFHR1 and PFHR2 transfers into the FIFO.
The timeout interrupt can be a general timer interrupt in the transmit direction. Unlike the receive
case, when DMAdir is true, the timeout status is immediately set when the timeout is triggered by a
‘0’-to-‘1’ transition of Stale. To use the timeout interrupt, the CPU must load the desired time delay
directly into the SDTCR. When the timer expires, Stale becomes true and the timeout interrupt is
generated.
CD1284 Parallel Port Overview
Terminology
This document uses the terms ‘master’ and ‘slave’ for the IEEE STD 1284 specification terms
‘host’ and ‘peripheral’ that describe the two sides of a parallel-port interface.
Signal Names
The IEEE STD 1284 specification uses different names for the nine control signals, depending on
the current mode of operation
names were selected to represent the most commonly used names of the various protocols. The
CD1284 device operates as a slave only. There are four input-control signals driven by the master-
side device, and five output-control signals driven by the slave-side device. The Parallel Data bus
(PD[7:0]) is bidirectional.
A_1284
HstBsy
HstClk
nInit
Names
Compatibility
AUTOFD*
STROBE*
SLCTIN*
INIT*
IEEE 1284-Compatible Parallel Interface Controller — CD1284
(Table
20). The CD1284 uses fixed names for each of its pins. The
Rev. NB
A_1284
HstBsy
HstClk
nInit
Inputs
Rev. BT
A_1284
HstBsy
HstClk
nInit
nRevReq
A_1284
HstAck
HstClk
ECP
nAStrb
nDStrb
nWrite
EPP
nInit
77