SCD128410QCE Intel, SCD128410QCE Datasheet - Page 125

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

7.4.3
Datasheet
Register Name: COR3
Register Description: Channel Option Register 3
Access: Read/Write
SCDRNG
Bit 7
Bit
Bit
4
3
2
1
0
7
6
Note: The threshold for the parallel channel (channel 0) are set by the PFTR.
Channel Option Register 3
Local Loopback Mode: This bit enables local loopback of the channel. This mode is generally used during
system diagnostics. If this bit is set, the transmitter is internally ‘looped’ back to the receiver. The TxD pin is
set to the marking state. Data sent is immediately received by the receiver. No data appears on the TxD pin;
data on the RxD pin is ignored.
Remote Loopback Mode: Remote loopback allows a remote system to test its serial data stream. If this
function is enabled, the CD1284 internally connects its receiver to the transmitter. Any data received is
immediately echoed back. This mode is enabled by setting RLM, and disabled by clearing RLM.
Request To Send Automatic Output: The CD1284 can automatically assert RTS when a channel is
enabled (by transmit/receive enable command in the CCR) and there is data in the FIFO. When the channel
is disabled or there is no more data to send (that is, in the FIFO or Holding and Shift registers), RTS* is
negated. Setting RtsAO enables the function.
Clear To Send Automatic Enable: This bit enables the CTS* input to control transmitter operation. If CtsAE
is set and CTS* is not asserted, character transmission does not proceed.
Data Set Ready Automatic Enable: This bit allows the DSR* input to control receiver operation. Setting
DsrAE enables the function. When enabled and DSR* is deasserted, the CD1284 discards all received
characters.
Special Character Detect Range: This bit enables range checking on received characters. If the character
falls between a lower range, set by the value stored in the SCRL register, and an upper range, set by the
value stored in the SCRH register – inclusive, a receive exception service request is posted with the status
indicating a range detect (RDSR bits SCDet2–SCDet0
Enable Special Character Detect on SCHR4 and SCHR3: This bit controls whether or not the CD1284
performs a comparison on received characters against the values stored in SCHR4 and SCHR3. The
comparison is enabled by this bit being ‘1’.
SCD34
Bit 6
Bit 5
FCT
IEEE 1284-Compatible Parallel Interface Controller — CD1284
SCD12
Bit 4
Description
Description
RxTh3
Bit 3
111).
RxTh2
Bit 2
RxTh1
Bit 1
8-Bit Hex Address: 0A
Default Value: 00
RxTh0
Bit 0
125