SCD128410QCE Intel, SCD128410QCE Datasheet - Page 136

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.6.10
7.7
7.7.1
136
Register Name: TCOR
Register Description: Transmit Clock Option
Access: Read/Write
Register Name: DER
Register Description: Data Error
Access: Read only
DMAwrerr
Bit 7
Bit 7
X
Transmit Clock Option Register
The TCOR selects the clock source which drives the TBPR. The value in ClkSel[2:0] selects one of
five possible clocks generated from the master clock (CLK).
Channel Registers — Parallel Pipeline
Data Error Register
The bits in this read-only register indicate read/write errors involving the DMABUF register and
the Data Pipeline registers. The DataErr bit (PFSR[0]) is the logical OR of these eight Error Status
bits.
Reading this register has no effect on the error status. A write to this register clears all the bits,
which cannot be written by the user. Host software should clear this register (write x’00) after
completing an error service-acknowledge procedure. This bit is provided primarily as an aid to
driver software development. Data errors should never occur under normal circumstances.
This register is cleared during device reset.
DMArderr
Bit 6
Bit 6
X
ClkSel2
0
0
0
0
1
1
1
1
Bufwrerr
Bit 5
Bit 5
X
ClkSel1
0
0
1
1
0
0
1
1
Bufrderr
Bit 4
Bit 4
X
ClkSel0
0
1
0
1
0
1
0
1
HR1wrerr
Bit 3
Bit 3
X
Clk0 (CLK
Clk1 (CLK
Clk2 (CLK
Clk3 (CLK
Clk4 (CLK
Not used.
HR1rderr
ClkSel2
Bit 2
Bit 2
8)
32)
128)
512)
2048)
Clock Selected
HR2wrerr
ClkSel1
Bit 1
Bit 1
8-Bit Hex Address: 76
8-Bit Hex Address: 33
Default Value: 01
Default Value: 00
Datasheet
HR2rderr
ClkSel0
Bit 0
Bit 0