SCD128410QCE Intel, SCD128410QCE Datasheet - Page 126

• Manufacturer Part Number: SCD128410QCE
• Manufacturer: Intel

Specifications of SCD128410QCE

• Pin Count: 100
• Lead Free Status / RoHS Status: Not Compliant

CD1284 — IEEE 1284-Compatible Parallel Interface Controller
7.4.4
126
Register Name: COR4
Register Description: Channel Option Register 4
Access: Read/Write
IGNCR
Bit 7
Bit
3:0
5
4
Channel Option Register 4
Flow Control Transparency: This bit enables/disables the transparent response to flow control characters
received by the CD1284. If set, received XON and XOFF characters are not placed in the FIFO for the host. If
in-band flow control is enabled, the characters are acted upon. If this bit is not set, flow control characters are
acted upon, placed in the receive FIFO, and the host is notified by a receive exception service request.
Enable Special Character Detect on SCHR2 and SCHR1: This bit controls whether or not the CD1284
compares received characters with the values stored in SCHR2 and SCHR1. ‘1’ enables compare. This bit
must be set to enable automatic in-band flow control.
Serial Receive FIFO Threshold
ICRNL
Bit 6
RxTh3
0
0
0
1
•
RxTh2
INLCR
Bit 5
0
0
0
0
•
RxTh1
0
0
1
1
•
IGNBRK
Bit 4
RxTh0
0
1
0
1
•
Description
BRKINT
Bit 3
Not used.
1 character
2 characters
11 characters
Receiver FIFO Threshold
PEH[2]
Bit 2
PEH[1]
Bit 1
8-Bit Hex Address: 1E
Default Value: 00
Datasheet
PEH[0]
Bit 0