ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 102

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 96.
ISP1161A1_5
Product data sheet
Bit
Symbol
Reset
Access
DcErrorCode register: bit allocation
13.2.7 Acknowledge Setup (F4H)
13.3.1 Read Endpoint Error Code (R: A0H–AFH)
UNREAD
13.3 General commands
R
7
0
Table 95.
This command acknowledges to the host that a Setup packet was received. The arrival of
a Setup packet disables the Validate Buffer and Clear Buffer commands for the control
IN and OUT endpoints. The microprocessor needs to re-enable these commands by
sending an Acknowledge Setup command, see
Code (Hex): F4 — acknowledge set-up
Transaction — none
This command returns the status of the last transaction of the selected endpoint, as stored
in the DcErrorCode register. Each new transaction overwrites the previous status
information. The bit allocation of the DcErrorCode register is shown in
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 word
Table 97.
Bit
3
2
1
0
Bit
7
6
DATA01
R
6
0
DcEndpointStatusImage register: bit description
DcErrorCode register: bit description
Symbol
OVERWRITE
SETUPT
CPUBUF
-
Symbol
UNREAD
DATA01
reserved
R
5
0
Rev. 05 — 29 September 2009
Description
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. If writing the
set-up data has finished, this bit is cleared by a read action.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1 the
firmware must stop ongoing set-up actions and wait for a new Setup
packet.
A logic 1 indicates that the buffer contains a Setup packet.
This bit indicates which buffer is currently selected for CPU access
(0 = primary buffer, 1 = secondary buffer).
reserved
Description
A logic 1 indicates that a new event occurred before the previous
status was read.
This bit indicates the PID type of the last successfully received or
transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).
R
4
0
USB single-chip host and device controller
R
3
0
ERROR[3:0]
Section
11.3.6.
R
2
0
…continued
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
R
1
0
Table
96.
RTOK
102 of 137
R
0
0