ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 47

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 12.
ISP1161A1_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcCommandStatus register: bit allocation
10.1.3 HcCommandStatus register (R/W: 02H/82H)
31
23
R
0
Table 11.
The HcCommandStatus register is used by the HC to receive commands issued by the
HCD, and it also reflects the HC’s current status. To the HCD, it appears to be a ‘write to
set’ register. The HC must ensure that bits written as logic 1 become set in the register
while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple
distinct commands to the HC without concern for corrupting previously issued commands.
The HCD has normal read access to all bits.
The SchedulingOverrunCount field indicates the number of frames with which the HC has
detected the scheduling overrun error. This occurs when the Periodic list does not
complete before EOF. When a scheduling overrun error is detected, the HC increments
the counter and sets the SchedulingOverrun field in the HcInterruptStatus register.
Code (Hex): 02 — read
Code (Hex): 82 — write
Bit
8
7 to 6
5 to 0
30
22
R
0
HcControl register: bit description
Symbol
-
HCFS
-
29
21
R
0
Rev. 05 — 29 September 2009
reserved
Description
reserved
HostControllerFunctionalState for USB:
00B — USBReset
01B — USBResume
10B — USBOperational
11B — USBSuspend
A transition to USBOperational from another state causes
start-of-frame (SOF) generation to begin 1 ms later. The HCD
determines whether the HC has begun sending SOFs by reading the
StartofFrame field of HcInterruptStatus.
This field can be changed by the HC only when in the USBSuspend
state. The HC can move from the USBSuspend state to the
USBResume state after detecting the resume signaling from a
downstream port.
The HC enters USBReset after a software reset and a hardware reset.
The latter also resets the Root Hub and asserts subsequent reset
signaling to downstream ports.
reserved
28
20
R
0
reserved
00H
R
USB single-chip host and device controller
…continued
27
19
R
0
26
18
R
0
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
25
17
R
0
SOC[1:0]
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24
16
R
0