ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 136

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

11.1.1
11.1.2
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.4
11.4.1
11.4.1.1
11.4.2
11.4.3
12
12.1
12.2
12.3
12.4
12.4.1
12.4.1.1
12.4.1.2
12.4.1.3
12.4.2
13
13.1
13.1.1
13.1.2
13.1.3
13.1.4
13.1.5
13.1.6
13.1.7
13.1.8
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
ISP1161A1_5
Product data sheet
DC DMA transfer . . . . . . . . . . . . . . . . . . . . . . . 84
DC commands and registers . . . . . . . . . . . . . 89
IN data transfer . . . . . . . . . . . . . . . . . . . . . . . . 76
OUT data transfer . . . . . . . . . . . . . . . . . . . . . . 76
Device DMA transfer . . . . . . . . . . . . . . . . . . . 77
DMA for IN endpoint (internal DC to external USB
host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DMA for OUT endpoint (external USB host to
internal DC) . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Endpoint descriptions . . . . . . . . . . . . . . . . . . . 78
Endpoints with programmable FIFO size . . . . 78
Endpoint access . . . . . . . . . . . . . . . . . . . . . . . 78
Endpoint FIFO size . . . . . . . . . . . . . . . . . . . . . 78
Endpoint initialization . . . . . . . . . . . . . . . . . . . 80
Endpoint I/O mode access . . . . . . . . . . . . . . . 80
Special actions on control endpoints . . . . . . . 80
Suspend and resume . . . . . . . . . . . . . . . . . . . 81
Suspend conditions . . . . . . . . . . . . . . . . . . . . 81
Powered-off application . . . . . . . . . . . . . . . . . 82
Resume conditions . . . . . . . . . . . . . . . . . . . . . 83
Control bits in suspend and resume . . . . . . . . 83
Selecting an endpoint for DMA transfer . . . . . 84
8237 compatible mode . . . . . . . . . . . . . . . . . . 85
DACK-only mode . . . . . . . . . . . . . . . . . . . . . . 86
End-Of-Transfer conditions. . . . . . . . . . . . . . . 87
Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . 87
External EOT . . . . . . . . . . . . . . . . . . . . . . . . . 87
DcDMACounter register . . . . . . . . . . . . . . . . . 88
Short packet . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Isochronous endpoints . . . . . . . . . . . . . . . . . . 88
Initialization commands . . . . . . . . . . . . . . . . . 91
DcEndpointConfiguration register (R/W:
30H–3FH/20H–2FH). . . . . . . . . . . . . . . . . . . . 91
DcAddress register (R/W: B7H/B6H) . . . . . . . 92
DcMode register (R/W: B9H/B8H) . . . . . . . . . 92
DcHardwareConfiguration register (R/W:
BBH/BAH). . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
DcInterruptEnable register (R/W: C3H/C2H) . 95
DcDMAConfiguration register (R/W: F1H/F0H) 96
DcDMACounter register (R/W: F3H/F2H). . . . 97
Reset Device (F6H) . . . . . . . . . . . . . . . . . . . . 98
Data flow commands . . . . . . . . . . . . . . . . . . . 98
Write/Read Endpoint Buffer (R/W:
10H,12H-1FH/01H–0FH) . . . . . . . . . . . . . . . . 98
DcEndpointStatus register (R: 50H–5FH). . . . 99
Stall Endpoint/Unstall Endpoint
(40H–4FH/80H—8FH) . . . . . . . . . . . . . . . . . 100
Validate Endpoint Buffer (R/W: 6FH/61H). . . 101
Clear Endpoint Buffer (70H, 72H–7FH) . . . . 101
DcEndpointStatusImage register(D0H–DFH) 101
Acknowledge Setup (F4H) . . . . . . . . . . . . . . 102
General commands . . . . . . . . . . . . . . . . . . . 102
Read Endpoint Error Code (R: A0H–AFH) . . 102
Unlock Device (B0H) . . . . . . . . . . . . . . . . . . 103
DcScratch register (R/W: B3H/B2H). . . . . . . 104
Read Frame Number (R: B4H) . . . . . . . . . . . 104
Read Chip ID (R: B5H) . . . . . . . . . . . . . . . . . 105
Read Interrupt register (R: C0H). . . . . . . . . . 106
Rev. 05 — 29 September 2009
14
15
16
17
18
19
20
20.1
20.1.1
20.1.2
20.2
20.2.1
20.2.2
20.2.3
20.2.4
20.2.5
20.2.6
20.2.7
20.2.8
20.2.9
20.2.10
21
21.1
21.2
21.3
22
23
24
25
26
27
Power supply. . . . . . . . . . . . . . . . . . . . . . . . . 108
Crystal oscillator and LazyClock . . . . . . . . . 108
Power-on reset (POR) . . . . . . . . . . . . . . . . . . . 111
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 112
Recommended operating conditions . . . . . . 112
Static characteristics . . . . . . . . . . . . . . . . . . . 113
Dynamic characteristics. . . . . . . . . . . . . . . . . 115
Application information . . . . . . . . . . . . . . . . 125
Test information . . . . . . . . . . . . . . . . . . . . . . 128
Package outline. . . . . . . . . . . . . . . . . . . . . . . 129
Revision history . . . . . . . . . . . . . . . . . . . . . . 131
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
USB single-chip host and device controller
Programmed I/O timing . . . . . . . . . . . . . . . . . 116
External EOT timing for HC single-cycle
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
External EOT timing for HC burst mode DMA 121
DC single-cycle DMA timing (8237 mode) . . 121
DC single-cycle DMA read timing in DACK-only
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
DC single-cycle DMA write timing in DACK-only
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
EOT timing in DC single-cycle DMA . . . . . . 123
EOT timing in DC burst mode DMA . . . . . . . 124
Typical interface circuit. . . . . . . . . . . . . . . . . 125
Interfacing a ISP1161A1 with a SH7709 RISC
processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Typical software model . . . . . . . . . . . . . . . . 126
HC Programmed I/O timing . . . . . . . . . . . . . . 116
DC Programmed I/O timing . . . . . . . . . . . . . . 117
DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 118
HC single-cycle DMA timing . . . . . . . . . . . . . 118
HC burst mode DMA timing . . . . . . . . . . . . . . 119
DC burst mode DMA timing . . . . . . . . . . . . . 123
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
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