ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 76

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

11. USB device controller (DC)
ISP1161A1_5
Product data sheet
11.1.1 IN data transfer
11.1.2 OUT data transfer
11.1 DC data transfer operation
The Device Controller (DC) in the ISP1161A1 is based on the ST-Ericsson ISP1181B USB
Full-Speed Interface Device IC. The functionality, commands, and register sets are the
same as ISP1181B in 16-bit bus mode. If there is any difference between the ISP1181B
and ISP1161A1 data sheets, in terms of the DC functionality, the ISP1161A1 data sheet
supersedes content in the ISP1181B data sheet.
In general the DC in an ISP1161A1 provides 16 endpoints for USB device
implementation. Each endpoint can be allocated an amount of RAM space in the on-chip
Ping-Pong buffer RAM.
Remark: The Ping-Pong buffer RAM for the DC is independent of the buffer RAM in
the HC.
When the buffer RAM is full, the DC will transfer the data in the buffer RAM to the USB
bus. When the buffer RAM is empty, an interrupt is generated to notify the microprocessor
to feed in the data. The transfer of data between the microprocessor and the DC can be
done in Programmed I/O (PIO) mode or in DMA mode.
The following session explains how the DC of an ISP1161A1 handles an IN data transfer
and an OUT data transfer. In the Device mode, the ISP1161A1 acts as a USB device: an
IN data transfer means transfer from the ISP1161A1 to an external USB Host (through the
upstream port) and an OUT transfer means transfer from external USB Host to the
ISP1161A1.
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The arrival of the IN token is detected by the SIE by decoding the PID.
The SIE also checks for the device number and endpoint number and verifies whether
they are acceptable.
If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus
register. If the endpoint is full, the contents of the FIFO are sent during the data phase,
otherwise a Not Acknowledge (NAK) handshake is sent.
After the data phase, the SIE expects a handshake (ACK) from the host (except for
ISO endpoints).
On receiving the handshake (ACK), the SIE updates the contents of the
DcEndpointStatus register and the DcInterrupt register, which in turn generates an
interrupt to the microprocessor. For ISO endpoints, the DcInterrupt register is updated
as soon as data is sent because there is no handshake phase.
On receiving an interrupt, the microprocessor reads the DcInterrupt register. It will
know which endpoint has generated the interrupt and reads the contents of the
corresponding DcEndpointStatus register. If the buffer is empty, it fills up the buffer, so
that data can be sent by the SIE at the next IN token phase.
The arrival of the OUT token is detected by the SIE by decoding the PID.
Rev. 05 — 29 September 2009
USB single-chip host and device controller
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
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