ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 95

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ISP1161A1_5
Product data sheet
13.1.5 DcInterruptEnable register (R/W: C3H/C2H)
Table 83.
This command is used to individually enable or disable interrupts from all endpoints, as
well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,
resume, reset). That is, if an interrupt event occurs while the interrupt is not enabled,
nothing will be seen on the interrupt pin. Even if you then enable the interrupt during the
interrupt event, there will still be no interrupt seen on the interrupt pin, see
The DcInterrupt register will not register any interrupt, if it is not already enabled using the
DcInterruptEnable register. The DcInterruptEnable register is not an Interrupt Mask
register.
A bus reset will not change any of the programmed bit values.
The command accesses the DcInterruptEnable register, which consists of 4 bytes. The bit
allocation is given in
Remark: For details on interrupt control, see
Code (Hex): C2/C3 — write/read DcInterruptEnable register
Transaction — write/read 2 words
Bit
2
1
0
Fig 42. Interrupt pin waveform.
Pin INT2: HIGH = de-assert; LOW = assert; INTENA = 1.
DcHardwareConfiguration register: bit description
Symbol
PWROFF
INTLVL
INTPOL
INT2 pin
Rev. 05 — 29 September 2009
Table
DcInterruptEnable
disabled
register
interrupt
occurs
84.
event
Description
A logic 1 enables powering-off during ‘suspend’ state. Output
D_SUSPEND pin is configured as a power switch control signal for
external devices (HIGH during ‘suspend’). This value should always
be initialized to logic 1. Bus reset value: unchanged.
Selects the interrupt signalling mode on output pin INT2 (0 = level,
1 = pulsed). In pulsed mode an interrupt produces an 166 ns pulse.
See
Selects INT2 pin signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
Section 8.6.3
DcInterruptEnable
enabled
register
USB single-chip host and device controller
for details. Bus reset value: unchanged.
Section
interrupt
occurs
event
8.6.3.
interrupt is cleared
…continued
004aaa197
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
Figure
42.
95 of 137