ISP1161A1BMGA STEricsson, ISP1161A1BMGA Datasheet - Page 135

• Manufacturer Part Number: ISP1161A1BMGA
• Manufacturer: STEricsson

Specifications of ISP1161A1BMGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

27. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
8
8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.3.1
9
9.1
9.2
9.3
9.3.1
9.4
9.4.1
9.4.2
9.4.3
9.5
9.5.1
9.5.2
9.6
9.7
9.8
9.8.1
9.8.2
ISP1161A1_5
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
Functional description . . . . . . . . . . . . . . . . . . 11
Microprocessor bus interface. . . . . . . . . . . . . 12
USB host controller (HC). . . . . . . . . . . . . . . . . 24
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
PLL clock multiplier. . . . . . . . . . . . . . . . . . . . . 11
Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . 11
Analog transceivers . . . . . . . . . . . . . . . . . . . . 11
ST-Ericsson Serial Interface Engine (SIE) . . . 11
SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . 11
GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Programmed I/O (PIO) addressing mode . . . . 12
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Control register access by PIO mode . . . . . . . 13
I/O port addressing . . . . . . . . . . . . . . . . . . . . . 13
Register access phases . . . . . . . . . . . . . . . . . 14
FIFO buffer RAM access by PIO mode . . . . . 16
FIFO buffer RAM access by DMA mode . . . . 17
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . 18
HC’s interrupt output pin (INT1) . . . . . . . . . . . 19
DC interrupt output pin (INT2) . . . . . . . . . . . . 21
Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 22
HC’s four USB states . . . . . . . . . . . . . . . . . . . 24
Generating USB traffic . . . . . . . . . . . . . . . . . . 24
PTD data structure . . . . . . . . . . . . . . . . . . . . . 26
PTD data header definition . . . . . . . . . . . . . . . 26
HC internal FIFO buffer RAM structure . . . . . 29
Partitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data organization . . . . . . . . . . . . . . . . . . . . . . 31
Operation and C program example . . . . . . . . 32
HC operational model . . . . . . . . . . . . . . . . . . . 36
Time domain behavior . . . . . . . . . . . . . . . . . . 37
Control transaction limitations. . . . . . . . . . . . . 38
Microprocessor loading . . . . . . . . . . . . . . . . . 38
Internal pull-down resistors for downstream
ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
OC detection and power switching control . . . 39
Using an internal OC detection circuit . . . . . . 40
Using an external OC detection circuit . . . . . . 41
Rev. 05 — 29 September 2009
9.9
9.9.1
9.9.2
9.9.2.1
9.9.2.2
9.9.2.3
10
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1.6
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.5
10.5.1
10.5.2
10.5.3
10.6
10.6.1
10.6.2
10.6.3
10.6.4
10.6.5
10.6.6
10.6.7
11
11.1
HC registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
USB device controller (DC) . . . . . . . . . . . . . . 76
USB single-chip host and device controller
Suspend and wake-up . . . . . . . . . . . . . . . . . . 41
HC suspended state . . . . . . . . . . . . . . . . . . . 41
HC wake-up from suspended state . . . . . . . . 42
Wake-up by pin H_WAKEUP . . . . . . . . . . . . . 42
Wake-up by pin CS (software wake-up). . . . . 43
Wake-up by USB devices . . . . . . . . . . . . . . . 43
HC control and status registers . . . . . . . . . . . 45
HcRevision register (R: 00H) . . . . . . . . . . . . . 45
HcCommandStatus register (R/W: 02H/82H). 47
HcInterruptStatus register (R/W: 03H/83H) . . 48
HcInterruptEnable register (R/W: 04H/84H). . 49
HcInterruptDisable register (R/W: 05H/85H) . 50
HC frame counter registers . . . . . . . . . . . . . . 52
HcFmInterval register (R/W: 0DH/8DH) . . . . . 52
HcFmRemaining register (R: 0EH) . . . . . . . . 53
HcLSThreshold register (R/W: 11H/91H) . . . . 54
HC Root Hub registers. . . . . . . . . . . . . . . . . . 55
HcRhDescriptorA register (R/W: 12H/92H) . . 56
HcRhDescriptorB register (R/W: 13H/93H) . . 57
HcRhPortStatus[1:2] register (R/W [1]:15H/95H,
[2]: 16H/96H) . . . . . . . . . . . . . . . . . . . . . . . . . 60
HC DMA and interrupt control registers . . . . . 63
HcHardwareConfiguration register (R/W:
20H/A0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
HcmPInterrupt register (R/W: 24H/A4H) . . . . 67
(R/W: 25H/A5H) . . . . . . . . . . . . . . . . . . . . . . . 68
HC miscellaneous registers . . . . . . . . . . . . . . 69
HcChipID register (R: 27H) . . . . . . . . . . . . . . 69
HcScratch register (R/W: 28H/A8H) . . . . . . . 69
HC buffer RAM control registers . . . . . . . . . . 71
HcITLBufferLength register (R/W: 2AH/AAH) 71
HcBufferStatus register (R: 2CH) . . . . . . . . . . 72
HcReadBackITL0Length register (R: 2DH) . . 73
HcReadBackITL1Length register (R: 2EH) . . 73
HcITLBufferPort register (R/W: 40H/C0H) . . . 74
DC data transfer operation. . . . . . . . . . . . . . . 76
HcControl register (R/W: 01H/81H) . . . . . . . . 46
HcFmNumber register (R: 0FH) . . . . . . . . . . . 53
HcRhStatus register (R/W: 14H/94H). . . . . . . 58
HcDMAConfiguration register (R/W: 21H/A1H) 64
HcTransferCounter register (R/W: 22H/A2H). 66
HcmPInterruptEnable register
HcSoftwareReset register (W: A9H) . . . . . . . 70
HcATLBufferLength register (R/W: 2BH/ABH) 71
HcATLBufferPort register (R/W: 41H/C1H) . . 74
ISP1161A1
© ST-ERICSSON 2009. All rights reserved.
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