LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 107

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.4.2 Initiator Command Complete Sequence
5.4.3 Message Accepted
This command causes the FSC to receive a status byte followed by a
message byte. It terminates early if the target does not assert the
Message In phase, or if the target disconnects. After receiving the
message byte, the FSC leaves ACK/ asserted on the bus to allow the
initiator to assert ATN/ if the message is unacceptable.
This command deasserts the ACK/ signal on the SCSI bus. Any of the
commands that receive bytes during message phase leave ACK/
asserted after receiving the last message byte. To accept the message,
issue this command. To reject the message, set ATN/ and then issue
this command.
Initiator Command Group
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
If the phase is Message Out, the FSC removes ATN/ prior to
asserting ACK/ for the last byte of the message. For non-DMA, the
FIFO flags indicate the last byte. For DMA, the transfer counter
indicates the last byte.
Target changes phase. The FSC clears the
generates a Bus Service interrupt after the target asserts REQ/ for
the next byte.
Target releases BSY/ (Busy). The FSC generates a Disconnected
interrupt.
The FSC receives the last byte of a Message In phase. (For
non-DMA, every byte is assumed to be the last byte. For DMA, the
transfer counter signals the last byte.) The FSC leaves ACK/
asserted and generates a Function Complete interrupt.
All Message In and Status phase transfers are handled one byte at
a time. If DMA is enabled, the next byte is not received until the
current byte has been written to buffer memory and the FIFO is
empty. If DMA is not enabled, each byte creates an interrupt.
Command
register and
5-15