LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 59

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Notes:
If two commands are placed in the command register, two interrupts may
result. If the first interrupt is not serviced before the second finishes, the
second interrupt is placed behind the first. The first interrupt must be
serviced before issuing a third command. When the
read by the host to service the first interrupt, the contents of the
Status
describe the second interrupt. When using stacked commands, the
Features Enable bit
latch the SCSI phase bit in the
stacked command.
ENDMA
CC
Standard Register Set
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Any phase change in initiator mode (except when issuing a
sequence command)
Illegal command
Non-DMA Send commands should not be stacked.
Commands that transfer data in one direction should not be stacked
with commands that transfer data in the opposite direction.
After a hardware reset or Reset Chip command, a NOP is required
to fill the Command register.
register,
Enable DMA
When bit 7 is set, the command is a DMA instruction.
When it is not set, the command is a non-DMA instruction.
DMA instructions load the internal byte counter with the
value in the Transfer Count register, without changing the
count register. If the transfer terminates prematurely, the
bits in the Status,
indicate why.
Command Code
The FSC commands are shown in
and 4 specify a mode group, as shown in the following
illustration. Commands from the miscellaneous group may
be issued at any time. Commands from the disconnected
target or initiator groups are only accepted by the FSC if
it is in the same mode as the command when it falls to
the bottom of the command FIFO. Otherwise, an illegal
command interrupt is generated. For example, after a
hardware or software reset, the FSC is in the
Sequence Step
(Configuration 2 (Config
Status
register, and
Sequence
register at the completion of each
Step, and
Interrupt
2), bit 6) should be set to
Table
Interrupt
register change to
Interrupt
5.1. Bits 6, 5,
register is
registers
[6:0]
4-9
7