LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 88

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4-38
ENSS
ADB
ARB
LL
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
not respond to this initial bus scan because of their
delayed response. After a SCAM slave has been
assigned an ID, this bit should be cleared to enable
normal selection response.
Enable SCAM Selection Response
When this bit is set, the FSC monitors the SCSI bus for
SCAM selections. When the FSC detects a valid SCAM
selection, it asserts SEL/ and MSG/, sets both the SEL
and SATN bits in the
interrupt pin.
Assert Data Bus
When set, this bit allows the contents of the
Data Latch (SODL)
outputs. Parity is also generated and asserted onto the
SCSI data bus. The Low Level Parity Control bit
determines whether the generated parity is even or odd.
Arbitrate
When set, this bit starts the arbitration process when a
bus-free condition has been detected. Prior to setting this
bit, the
contain the proper SCSI ID value. One SCSI ID bit should
be set for normal low-level arbitration; no ID bits should be
set for SCAM arbitration without an ID. The chip waits for
a bus-free condition before entering the arbitration phase.
The status of the arbitration phase may be determined by
reading the SCSI
Low Level
Setting this bit places the FSC into low-level mode. In this
mode, direct control of the SCSI bus is possible. SCSI
bus arbitration, selection, and data transfers are
performed by manually asserting and monitoring
SCS bus signals. When this bit is cleared, both the
SCSI Output Control Latch (SOCL)
Data Latch (SODL)
bus status using the
SCSI Bus Data Lines (SBDL)
regardless of the state of this bit.
SCSI Output Data Latch (SODL)
Status
registers are held reset. The current
register to be enabled as chip
SCSI Bus Control Lines (SBCL)
Interrupt
register, bits [1:0].
registers is available
register, and asserts the
and
register should
SCSI Output
SCSI Output
and
3
2
1
0