LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 68

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LSI53CF92A-64QFP

Manufacturer Part Number
LSI53CF92A-64QFP
Description
Manufacturer
LSI
Datasheet

Specifications of LSI53CF92A-64QFP

Lead Free Status / RoHS Status
Supplier Unconfirmed
4-18
Register: 0x06
Synchronous Transfer Period
Write Only
Register Bank 0 or 1
Bits [4:0] of this register specify the minimum time between leading
edges of successive REQ/ (Request) or ACK/ (Acknowledge) pulses.
Synchronous data is transmitted or received at the rate of one byte every
“n” Clocks (CLK). The variable “n” is related to the register value and the
data transfer rate as shown in
Registers
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
7
0
R
0
5
0
4
0
Table 4.3
Default
3
0
and
Clocks Per Byte
Table
2
1
4.4.
1
0
0
1

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