LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 29

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.4.3 Nonmultiplexed Bus Configuration Mode
2.5 DMA Operation
2.5.1 DMA Threshold
2.5.2 Normal DMA Mode
Like the Multiplexed Bus Configuration mode, this dual bus mode is
configured for 8-bit transfers.
In this dual bus mode interface, DMA operations are supported by the
DB bus, and the microprocessor interface is supported by the PAD bus.
FIFO parity is not available for data transfers over the PAD bus. The
direction of transfer is determined by the RD/ and WR/ lines. CS/ must
be active during PAD bus accesses.
In the Nonmultiplexed Bus Configuration mode, transfers occur on the
microprocessor interface over the PAD bus, which operates as a
nonmultiplexed data only bus. The register address is carried by the A[3:0]
lines and is latched into the chip on the HIGH to LOW transition of CS/.
The FSC supports 8-bit DMA transfers. The on-chip FIFO allows the FSC
to support normal and burst mode transfers. The DMA interface protocol
runs asynchronous to the chip clock. The DMA Request signal (DREQ) is
asserted when the DMA is ready for a transfer to or from the DMA channel.
DREQ is asserted only when the DMA Acknowledge signal (DACK/) is
inactive, and is released on the leading edge of DACK/. DREQ remains
asserted until the chip receives as many DACK/s as it needs or can handle.
The threshold is the number of bytes in the FIFO that trigger DREQ. For
DMA read, DREQ is asserted when the FIFO contains at least the
threshold number of bytes. For DMA write, the FIFO must be able to
accept this number of bytes. For 8-bit DMA operation the normal
threshold is one byte.
In normal operation, DREQ remains true until the FIFO empties or fills,
depending on the direction of the transfer.
where the threshold is always exceeded. This is typical of a DMA interface
that is slower than the SCSI device to which the system is connected.
DMA Operation
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Figure 2.1
illustrates the case
2-9