LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 39

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.8.2.2 SCAM Selection
Step 3. Set the ARB bit.
Step 4. Wait for the ARB1 status bit (normal arbitration) or the ARB4
After arbitration is complete as described in Section 2.8.2.1, BSY/ and
SEL/ are asserted on the bus. The following steps should be performed
by software to generate a SCAM selection:
Step 1. Assert MSG/ using the
Step 2. Delay at least two de-skew delays, then release BSY/ using the
Step 3. Maintain SEL/ and MSG/ asserted with BSY/ released for a
Step 4. Wait until MSG/ has been released by all other devices
SCAM Capabilities
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Note:
Note:
status bit (SCAM, no ID).
Examine the bus (read
IF (any device with higher ID is present) then
another device has won arbitration
turn off ARB and Low Level
goto Step 1
ELSE
arbitration has been won
assert BSY, SEL using SOCL register
turn off ARB bit
ENDIF
register.
SCSI Output Control Latch (SOCL)
minimum of a SCAM selection response time, then release MSG/.
(examine the
wired-OR glitch filtering in software.
If another device wins arbitration and asserts SEL/, the
FSC deasserts BSY/ and rearbitrates the next time a bus
free condition is detected. The FSC continues arbitrating
until either it wins (ARB1, ARB4 set and no higher IDs on
the bus) or until the ARB bit is reset.
The SCAM specification provides for two distinctly different
SCAM selection response times; the long SCAM selection
response time (250 ms), and the short SCAM selection
response time (1 ms). Many Level 2 SCAM systems can
accommodate the 1 ms SCAM selection response time.
SCSI Bus Control Lines (SBCL)
SCSI Bus Data Lines
SCSI Output Control Latch (SOCL)
register.
(SBDL))
register), using
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