LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 46

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 3.1
3-2
Name
PAD[7:0]
DB[7:0]
DBP
A0
A1
A2-DBRD/
A3-ALE
DBWR/
CS/
RD/
Microprocessor and DMA Interface Signals
Bump
63–60
58–55
15–14
12–10
8-6
16
49
50
52
53
4
47
46
Table 3.1
Signal Descriptions
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
lists the Microprocessor and DMA Interface Signals group.
Type
B
B
B
I
I
I
I
Description
Bidirectional, active HIGH processor address-data
bus with internal 200 A pull-ups. These pins allow
the processor to access the internal registers of the
chip at the same time the DMA bus is active. In
multiplexed mode, address and data share this bus.
In nonmultiplexed mode, these pins are for data only.
Bidirectional, active HIGH data bus with internal
200 A pull-ups. These pins are the 8-bit DMA
data bus.
Odd parity for DB[7:0].
In nonmultiplexed mode, these TTL-compatible inputs
are address bits [3:0]. In multiplexed mode, they
become A0, A1, DBRD/, and ALE. The address on
the PAD bus is internally latched when ALE switches
from HIGH to LOW. DBRD/ is the read signal for the
DB bus. Also, in multiplexed mode, A1 and A0 must
be tied to V
Active LOW, DMA write signal which strobes DB[7:0]
data into the FIFO when DACK/ is true.
Active LOW chip select. This TTL-compatible input
enables eight-bit access to internal registers during
read or write. CS/ uses the address inputs to access
any register (including the FlFO) while DACK/
accesses only the FIFO. CS/ and DACK/ may both be
true at the same time, provided that CS/ is not
accessing the FIFO.
Active LOW register read signal. This TTL-compatible
input allows internal registers to drive the data bus
when CS/ is also true.
SS
to transfer data on DB[7:0].