LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 35

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.7 Chip Reset
2.7.1 Hard Reset
Table 2.2
To support maximum Fast SCSI transfer rates and SCSI-1 transfer
requirements, the FASTSCSI (bit 4) and FASTCLK (bit 3) bits have been
added to the
state machine to provide fast and normal synchronous timings depending
upon the clock frequency. A full description of the operations of these bits
and the required clock frequencies are provided in the
(Config 3)
During synchronous SCSI transfers, the assertion and deassertion of the
REQ/ and ACK/ signals is programmable using the FASTCLK bit and
other bits in the Synchronous Offset register. The input clock duty cycle
affects the half clock assertion/deassertion delays. For more information,
see the
The FSC has the following three levels of reset:
A hard reset is executed, when using the Reset Chip command, or when
the RESET pin is asserted by external hardware. It stops all chip
operations, resets all functions in the chip, and returns the chip to a
disconnected state. The Reset Chip command remains at the top of the
Command
state until a NOP command is issued. At power up, the RESET pin must
be asserted as V
Chip Reset
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Mode
SCSI-1
SE Fast SCSI-2
Hard
Soft
Disconnect
Synchronous Offset
register description in
register FIFO, which locks the chip and all registers in a reset
Minimum Timing Requirements
Configuration 3 (Config 3)
DD
first becomes stable.
Setup
55 ns
25 ns
register description in
Chapter 4, “Registers.”
100 ns
35 ns
Hold
register. They modify the SCSI
Assert/Negate
90 ns
30 ns
Chapter 4, “Registers.”
Configuration 3
2-15