MC9S08QG8CPBE Freescale, MC9S08QG8CPBE Datasheet - Page 171

MC9S08QG8CPBE

Manufacturer Part Number
MC9S08QG8CPBE
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9S08QG8CPBE

Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
16
Package Type
PDIP
Program Memory Type
Flash
Program Memory Size
8KB
Lead Free Status / RoHS Status
Compliant

Available stocks

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Manufacturer
Quantity
Price
Part Number:
MC9S08QG8CPBE
Manufacturer:
CYPRESS
Quantity:
310
Part Number:
MC9S08QG8CPBE
0
11.6.1
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion
of byte transfer.
11.6.2
When the calling address matches the programmed slave address (IIC address register), the IAAS bit in
the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW
bit and set its Tx mode accordingly.
11.6.3
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
This bit must be cleared by software by writing a one to it.
Freescale Semiconductor
SDA sampled as a low when the master drives a high during an address or data transmit cycle.
SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
A START cycle is attempted when the bus is busy.
A repeated START cycle is requested in slave mode.
A STOP condition is detected when the master did not request it.
Byte Transfer Interrupt
Address Detect Interrupt
Arbitration Lost Interrupt
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Inter-Integrated Circuit (S08IICV1)
169

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