MC9S08QG8CPBE Freescale, MC9S08QG8CPBE Datasheet - Page 81
MC9S08QG8CPBE
Manufacturer Part Number
MC9S08QG8CPBE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08QG8CPBE.pdf
(314 pages)
Specifications of MC9S08QG8CPBE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
16
Package Type
PDIP
Program Memory Type
Flash
Program Memory Size
8KB
Lead Free Status / RoHS Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
CYPRESS
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2
6.3
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
6.4
6.4.1
This section provides information about the registers associated with the parallel I/O ports.
Refer to tables in
for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.4.1.1
Freescale Semiconductor
Reset:
Reads of bit PTAD5 always return the pin value of PTA5, regardless of the value stored in bit PTADD5.
Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4.
•
•
•
W
R
In stop1 mode, all internal registers including parallel I/O control and data registers are powered
off. Each of the pins assumes its default reset state (output buffer and internal pullup disabled).
Upon exit from stop1, all pins must be re-configured the same as if the MCU had been reset by
POR.
Stop2 mode is a partial power-down mode, whereby latches maintain the pin state as before the
STOP instruction was executed. CPU register status and the state of I/O registers must be saved in
RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon recovery
from stop2 mode, before accessing any I/O, the user must examine the state of the PPDF bit in the
SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had occurred.
If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was executed,
and peripherals previously enabled will require being initialized and restored to their pre-stop
condition. The user must then write a 1 to the PPDACK bit in the SPMSC2 register. Access of pins
is now permitted again in the user application program.
In stop3 mode, all pin states are maintained because internal logic stays powered up. Upon
recovery, all pin functions are the same as before entering stop3.
Pin Behavior in Stop Modes
Parallel I/O Registers
Port A Registers
Port A Data (PTAD)
0
7
0
Chapter 4, “Memory Map and Register
0
0
6
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Figure 6-2. Port A Data Register (PTAD)
PTAD5
0
5
1
PTAD4
0
4
2
Definition,” for the absolute address assignments
PTAD3
3
0
PTAD2
Chapter 6 Parallel Input/Output Control
0
2
PTAD1
0
1
PTAD0
0
0
79
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