ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 183

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.89 Bus Controller Configuration 0 MSR (BC_CONFIG0_MSR)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:28
27:24
23:21
Bits
Bit
20
5
4
3
2
1
0
RSVD
Name
RETEN_TLB
RUN_TLB
RETEN_DATA
RUN_DATA
RETEN_TAG
RUN_TAG
Name
RSVD
PAUSEDLY
RSVD
GPF_X
PAUSEDLY
00001900h
R/W
00000000_00000111h
Description
L2 TLB Retention Timer. Enable retention timer for L2 TLB BIST.
0: Disable.
1: Enable.
L2 TLB Run. Start BIST test on L2 TLB arrays. Should read as 0 because BIST will have
completed before the MSR read can start.
Cache Data Retention Timer. Enable retention timer for cache data array BIST.
0: Disable.
1: Enable.
Cache Data Run. Start BIST test on cache data array. Should read as 0 because BIST will
have completed before the MSR read can start.
Cache Tag Retention Timer. Enable retention timer for cache tag array BIST.
0: Disable.
1: Enable.
Cache Tag Run. Start BIST test on cache tag arrays. Should read as 0 because BIST will
have completed before the MSR read can start.
Description
Reserved. Write as read.
Pause Delay. This field sets the number of clocks for which the bus controller will attempt
to suspend the CPU when a PAUSE instruction is executed. The approximate number of
clocks is PAUSEDLY*8. NOTE that the actual number of clocks that the CPU is sus-
pended will differ from this value, and will vary from pause to pause due to the overhead
of the suspend/unsuspend mechanism and any other CPU activity that would affect how
it responds to suspend requests.
Note also that bit 1 of MSR 00001210h must be set in order for suspend on pause to be
enabled.
Reserved.
General Protection Faults on EXCEPT Flags. Generate general protection faults on
MSR accesses whose response packets have the EXCEPT flag set.
0: Disable.
1: Enable.
RSVD
BC_CONFIG0_MSR Bit Descriptions
BC_CONFIG0_MSR Register Map
DM_BIST_MSR Bit Descriptions
RSVD
RSVD
RSVD
9
8
33234H
7
6
5
4
RSVD
3
2
1
183
0