ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 63

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GLIU Register Descriptions
4.2.2.5
MSR Address
Type
Reset Value
AERR is a condensed version of the port ERR signals. The MASK bits can be used to prevent a device from issuing an
AERR. If the MASK = 1, the device’s AERR is disabled.
AMD Geode™ LX Processors Data Book
63:16
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Asynchronous ERR (AERR)
Name
RSVD
ASMI_MASK7
ASMI_MASK6
ASMI_MASK5
ASMI_MASK4
ASMI_MASK3
ASMI_MASK2
ASMI_MASK1
ASMI_MASK0
ASMI_FLAG7
(RO)
ASMI_FLAG6
(RO)
ASMI_FLAG5
(RO)
ASMI_FLAG4
(RO)
ASMI_FLAG3
(RO)
ASMI_FLAG2
(RO)
ASMI_FLAG1
(RO)
ASMI_FLAG0
(RO)
GLIU0: 10000084h
GLIU1: 40000084h
R/W
00000000_00000000h
Description
Reserved.
Asynchronous SMI Mask for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.) Write 0 to
allow Port 7 to generate an ASMI. ASMI status is reported in bit 7.
Asynchronous SMI Mask for Port 6. (GLIU0 = Not Used; GLIU1 = SB.) Write 0 to allow
Port 6 to generate an ASMI. ASMI status is reported in bit 6.
Asynchronous SMI Mask for Port 5. (GLIU0 = GP; GLIU1 = VIP.) Write 0 to allow Port 5
to generate an ASMI. ASMI status is reported in bit 5.
Asynchronous SMI Mask for Port 4. (GLIU0 = DC; GLIU1 = GLPCI.) Write 0 to allow
Port 4 to generate an ASMI. ASMI status is reported in bit 4.
Asynchronous SMI Mask for Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.) Write 0 to
allow Port 3 to generate an ASMI. ASMI status is reported in bit 3.
Asynchronous SMI Mask for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.) Write 0
to allow Port 2 to generate an ASMI. ASMI status is reported in bit 2.
Asynchronous SMI Mask for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
Write 0 to allow Port 1 to generate an ASMI. ASMI status is reported in bit 1.
Asynchronous SMI Mask for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.) Write 0 to allow
Port 0 to generate an ASMI. ASMI status is reported in bit 0.
Asynchronous SMI Flag for Port 7 (Read Only). (GLIU0 = Not Used; GLIU1 = Not
Used.). If 1, this bit indicates that an ASMI was generated by Port 7. Cleared by source.
Asynchronous SMI Flag for Port 6 (Read Only). (GLIU0 = Not Used; GLIU1 = SB.) If 1,
this bit indicates that an ASMI was generated by Port 6. Cleared by source.
Asynchronous SMI Flag for Port 5 (Read Only). (GLIU0 = GP; GLIU1 = VIP.) If 1, this
bit indicates that an ASMI was generated by Port 5. Cleared by source.
Asynchronous SMI Flag for Port 4 (Read Only). (GLIU0 = DC; GLIU1 = GLPCI.) If 1,
this bit indicates that an ASMI was generated by Port 4. Cleared by source.
Asynchronous SMI Flag for Port 3 (Read Only). (GLIU0 = CPU Core; GLIU1 = GLCP.)
If 1, this bit indicates that an ASMI was generated by Port37. Cleared by source.
Asynchronous SMI Flag for Port 2 (Read Only). (GLIU0 = Interface to GLIU1; GLIU1 =
VP.) If 1, this bit indicates that an ASMI was generated by Port 2. Cleared by source.
Asynchronous SMI Flag for Port 1 (Read Only). (GLIU0 = GLMC; GLIU1 = Interface to
GLIU0.) If 1, this bit indicates that an ASMI was generated by Port 1. Cleared by source.
Asynchronous SMI Flag for Port 0 (Read Only). (GLIU0 = GLIU; GLIU1 = GLIU.) If 1,
this bit indicates that an ASMI was generated by Port 0. Cleared by source.
ASMI Bit Descriptions
33234H
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