ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 191

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
AMD Geode™ LX Processors Data Book
Bit
10
9
8
7
6
5
4
3
2
1
0
Name
BIST_TAG_GO_
WAY3 (RO)
BIST_TAG_GO_
WAY2 (RO)
BIST_TAG_GO_
WAY1 (RO)
BIST_TAG_GO_
WAY0 (RO)
BIST_TAG_GO
(RO)
BIST_MRU_DRT_
EN
BIST_MRU_EN
BIST_DATA_
DRT_EN
BIST_DATA_EN
BIST_TAG_
DRT_EN
BIST_TAG_EN
L2_BIST_MSR Bit Descriptions (Continued)
Description
L2 Cache Tag BIST Way 3 Result (Read Only).
0: Fail. (Default)
1: Pass.
L2 Cache Tag BIST Way 2 Result (Read Only).
0: Fail. (Default)
1: Pass.
L2 Cache Tag BIST Way 1 Result (Read Only).
0: Fail. (Default)
1: Pass.
L2 Cache Tag BIST Way 0 Result (Read Only).
0: Fail. (Default)
1: Pass.
L2 Cache Tag BIST Result (Read Only).
0: Fail. (Default)
1: Pass.
L2 Cache Most Recently Used Data Retention Timer BIST Enable. Enable the
data retention timer for the MRU BIST.
0: Disable. (Default)
1: Enable
L2 Cache Most Recently Used BIST Enable. Start MRU BIST (on a write).
0: Disable. (Default)
1: Enable
L2 Cache Data Retention Timer BIST Enable. Enable data retention timer for the
data BIST.
0: Disable. (Default)
1: Enable
L2 Cache Data BIST Enable. Start data BIST (on a write).
0: Don’t start BIST. (Default)
1: Start BIST
L2 Cache Tag Data Retention Timer BIST Enable. Enable Data Retention timer for
the Tag BIST.
0: Disable. (Default)
1: Enable
L2 Cache Tag BIST Enable. Start Tag BIST (on a write).
0: Don’t start BIST. (Default)
1: Start BIST
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