ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 500

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2.14 VIP Task A U Offset (VIP_TASK_A_U_OFFSET)
VIP Memory Offset 34h
Type
Reset Value
6.10.2.15 VIP Task B Video Even Base/Horizontal End (VIP_TASK_B_VID_EVEN_BASE_HORIZ_END)
VIP Memory Offset 38h
Type
Reset Value
500
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:0
31:0
15:0
Bit
Bit
Name
Task A U Odd
Offset
Name
TASK_B_VID_
EVEN_BASE
HORIZ_END
R/W
00000000h
R/W
00000000h
33234H
VIP_TASK_B_VID_EVEN_BASE_HORIZ_END Bit Descriptions
VIP_TASK_B_VID_EVEN_BASE_HORIZ_END Register Map
Description
Task A U Odd Offset. This register determines the starting address of the U buffer when
data is stored in planar format. For interlaced input, this register will determine the start-
ing address of the U data for the odd field. The start of the U buffer is determined by add-
ing the contents of this register to that of the base address. This value needs to be 32-
byte aligned. (Bits [4:0] are required to be 00000.)
Description
Task B Video Even Base Address. This register specifies the base address in graphics
memory where even video field data are stored. Changes to this register take effect at
the beginning of the next field. The value in this register is 16-byte aligned. Bits [3:0] are
always 0, and define the required address space.
Note:
Horizontal End. This register is redefined in BT.601 mode. In BT. 601 type input modes
timing is derived from the external HSYNC and VSYNC inputs. This value specifies
where video data ends for the line.
TASK_B_VID_EVEN_BASE_HORIZ_END (601 type modes)
VIP_TASK_A_U_OFFSET Bit Descriptions
VIP_TASK_A_U_OFFSET Register Map
This register is double buffered. When a new value is written to this register, the
new value is placed in a special pending register, and the Base Register Not
Updated bit (VIP Memory Offset 08h[16]) is set to 1. The Task B Video Even
Base Address register is not updated at this point. When the first data of the next
field is captured, the pending values of all base registers are written to the appro-
priate base registers, and the Base Register Not Updated bit is cleared.
Task A U Odd Offset
AMD Geode™ LX Processors Data Book
Video Input Port Register Descriptions
9
9
8
8
7
7
6
6
5
5
4
4
Program to 00000
3
3
2
2
1
1
0
0