ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 330

• Manufacturer Part Number: ALXD800EEXJ2VD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.5.4
DC Memory Offset 050h
Type
Reset Value
This register contains vertical active and total timing information. The parameters pertain to both CRT and flat panel display.
All values are specified in lines.
330
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
15:12
31:27
26:16
15:11
11:0
10:0
Bit
Bit
RSVD
DC Vertical and Total Timing (DC_V_ACTIVE_TIMING)
Name
RSVD
H_SYNC_ST
Name
RSVD
V_TOTAL
RSVD
V_ACTIVE
R/W
xxxxxxxxh
33234H
Description
Reserved. These bits should be programmed to zero.
Horizontal Sync Start. This field represents the pixel clock count at which the CRT hori-
zontal sync signal becomes active minus 1.
Unlike previous versions of the DC, this field can be programmed to any pixel granularity;
it is not limited to character (8-pixel) granularity.
The horizontal sync must be at least 8 pixels in width, and cannot begin until at least 8
pixels after H_BLK_START (DC Memory Offset 044h[11:0]).
Description
Reserved. These bits should be programmed to zero.
Vertical Total. This field represents the total number of lines for a given frame scan
minus 1. Note that the value is necessarily greater than the V_ACTIVE field (bits [10:0])
because it includes border lines and blanked lines. If the display is interlaced, the total
number of lines must be odd, so this value should be an even number.
Reserved. These bits should be programmed to zero.
Vertical Active. This field represents the total number of lines for the displayed portion of
a frame scan minus 1. Note that for flat panels, if this value is less than the panel active
vertical resolution (V_PANEL), the parameters V_BLANK_START, V_BLANK_END (DC
Memory Offset 054h[10:0, 26:16]), V_SYNC_START, and V_SYNC_END (DC Memory
Offset 058h[10:0, 26:16]) should be reduced by the following value (V_ADJUST) to
achieve vertical centering:
If the display is interlaced, the number of active lines should be even, so this value
should be an odd number.
If graphics scaling is enabled (and interleaved display is disabled), this value represents
the height of the final (scaled) image to be displayed. The height of the frame buffer
image may be different in this case; DC_FB_ACTIVE (DC Memory Offset 05Ch) is used
to program the horizontal and vertical active values in the frame buffer when graphics
scaling is enabled.
If interleaved mode is enabled, this value represents half the height of the final (scaled
and interleaved) displayed image.
V_TOTAL
DC_V_ACTIVE_TIMING Bit Descriptions
DC_H_SYNC_TIMING Bit Descriptions
DC_V_ACTIVE_TIMING Register Map
V_ADJUST = (V_PANEL - V_ACTIVE) / 2
RSVD
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
8
7
V_ACTIVE
6
5
4
3
2
1
0