ALXD800EEXJ2VD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD C3 Datasheet - Page 420

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ALXD800EEXJ2VD C3

Manufacturer Part Number
ALXD800EEXJ2VD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJ2VD C3

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
6.8.2.2
MSR Address
Type
Reset Value
420
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:40
37:0
Bit
39
38
Pad Select MSR (MSR_PADSEL)
RSVD
VOPCINV
RSVD
PADS
Name
48002011h
R/W
00000000_00000000h
33234H
Description
Reserved.
Invert VOP Clock. This is used to invert the VOP output clock. This may be used to meet
system timing requirements.
0: Non-inverted.
1: Inverted.
Reserved.
Select for Registered or Non-Registered VP Outputs. Bits select whether to use the
registers in the pad logic. The reset value of 38’b0 is valid for TFT 2 pixel per clock and
CRT mode.
Bits [37:30]: DF_DRGB[31:24]
0: Registered output.
1: Direct output.
Bit 29: RSVD.
Always write 0.
Bit 28: DF_DCLK
Bit 27: DF_DISP_EN
Bit 26: DF_LDE
Bit 25: DF_VSYNC
Bit 24: DF_HSYNC
Bits [23:0]: DF_DRGB[23:0]
0: Registered output.
1: Direct output.
MSR_PADSEL Bit Descriptions
RSVD
MSR_PADSEL Register Map
DF_DRGB[23:0]
AMD Geode™ LX Processors Data Book
Video Processor Register Descriptions
9
8
7
6
5
DF_DRGB[31:26]
4
3
2
1
0

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