PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 238

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
rate vertical scaling step is eliminated at the expense of
some quality since the lines are simply duplicated rather
than being fully scaled and filtered.
The OEN bit enables overlay. Set it to ‘1’ if an overlay is
used, ‘0’ if not. Overlays are only valid for PCI output.
The PCI bit selects PCI as the output port for the ICP da-
ta. A ‘1’ selects PCI output; a ‘0’ selects SDRAM output.
The BEN bit enables bit masking. Set it to ‘1’ if bit mask-
ing is used, ‘0’ if not. Bit masking is only valid for PCI out-
put.
The GETB bit is an optional bit for large (> 4) down scal-
ing. When GETB is ‘0’ (normal operation), the 5-tap filter
receives the pixel nearest the output pixel as its center
pixel plus the two adjacent input pixels on either side of
this pixel to form the five filter inputs. When GETB is set,
the filter receives the pixel nearest the output pixel as its
center pixel plus the two adjacent output pixels on either
side of this pixel to form the five filter inputs. The effective
algorithm is pixel picking plus 5-tap filtering of the result.
GETB also forces the scaling LSB value to ‘0’, since out-
put pixels are being filtered and no interpolation is used.
14-28
PRELIMINARY SPECIFICATION
The OFRM bit field selects the overlay data format, as
shown in the Control word format list.
The CHK bit enables chroma keying. Set it to ‘1’ if chro-
ma keying is used, ‘0’ if not.
The OLLE bit sets the endian-ness of the overlay data in-
put. Set it to ‘1’ if the overlay data is little-endian, ‘0’ if big
endian. This bit is normally set to the same value as the
LE bit in the Status register.
The LE bit sets the endian-ness of the RGB/YUV output
data. Set it to ‘1’ if the output data is little-endian, ‘0’ if big
endian. The LE bit is normally set to the same value as
the LE bit in the Status register.
The RGB field defines the output data format, as shown
in the Control word format list.
Important Note: The ICP DMA Enable bit (IE) in the
BIU_CTL register of the PCI interface must be set for
RGB output to PCI. This bit must be set before initiating
RGB to PCI operations, or the ICP will stall waiting for the
PCI to become ready.
Philips Semiconductors