PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 543

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

V.34 modem
vectored interrupts
vendor ID
vertical filter
vertical filter parameter table
vertical filtering
vertical scaling 14-1,
VI_BASE1
VI_BASE2
VI_CAP_SIZE
VI_CAP_START
VI_CLK
VI_CLOCK
VI_CTL
VI_DATA
VI_DATA[7:0]
VI_DATA[9:8]
VI_DVALID
VI_SIZE
VI_STATUS
VI_U_BASE_ADR
VI_UV_DELTA
VI_V_BASE_ADR
VI_Y_BASE_ADR
VI_Y_DELTA
victim of replacement
video image data formats
video in unit
A B C
PCI interface register
ICP
alignment
picture
alignment
picture
picture
picture
description table
picture 6-8,
picture 6-8,
VI_DATA[8]
VI_DATA[9]
description table
description table
description table
picture
picture 6-8,
picture
picture
picture
picture
picture
capture parameters
14-24
17-1, 17-2,
6-10
6-10
6-8
6-8
6-10
6-8
6-8
6-8
6-8
6-8
17-1
D
6-11
6-11
14-1
6-10
6-10
6-10
6-11
6-11
E
3-9
14-13
5-4
6-2
6-2
6-2
6-2
17-3
F G
7-9
11-3
14-24
H
I
J
K
L M N O P Q R S T U V W X Y Z
virtual registers
VLD
PRELIMINARY SPECIFICATION
clock generator
clocking modes
common source parameters
connected to 10bit A/D converter
connected to 8bit CCIR656 camera
connected to video out
connected to video recorder
co-sited sampling
diagnostic mode
format of SAV and EAV codes
fullres capture mode
halfres capture mode
halfres co-sited sample capture
halfres interspersed sample capture
halfres planar memory format
highway latency requirements
highway latency,HBE description
interface pins
interspersed sampling
message passing
message passing mode
message-passing mode
power down
raw and message passing modes
raw capture modes
raw mode,major states,diagram
raw10s capture mode
raw10u capture mode
raw8 capture mode
reset
YUV 4:2:2 planar memory format
YUV capture view of MMIO registers
explanation
picture
picture
picture
picture
picture
description
description
picture
picture
picture
description table
major states diagram
description
example signal diagram
description
MMIO register view, picture
description
picture
6-2
18-4
6-5
6-4
6-3
6-3
6-3
6-9
6-9
6-9
6-7
6-2
6-4
6-4
6-4
6-9
6-11
6-11
6-10
6-2
6-6
6-4
6-1
6-1
6-1
6-2
6-1
6-1
6-5
6-1
6-12
6-6
6-12
6-13
6-5
6-11
6-10
6-13
6-8
Index-17