PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 29

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
MM_CLK0
MM_CLK1
MM_A00
MM_A01
MM_A02
MM_A03
MM_A04
MM_A05
MM_A06
MM_A07
MM_A08
MM_A09
MM_A10
MM_A11
MM_A12
MM_A13
MM_DQ00
MM_DQ01
MM_DQ02
MM_DQ03
MM_DQ04
MM_DQ05
MM_DQ06
MM_DQ07
MM_DQ08
MM_DQ09
MM_DQ10
MM_DQ11
MM_DQ12
MM_DQ13
MM_DQ14
MM_DQ15
MM_DQ16
MM_DQ17
MM_DQ18
MM_DQ19
MM_DQ20
MM_DQ21
MM_DQ22
MM_DQ23
MM_DQ24
MM_DQ25
MM_DQ26
MM_DQ27
MM_DQ28
MM_DQ29
MM_DQ30
MM_DQ31
MM_CKE0
MM_CKE1
MM_CS0#
MM_CS1#
MM_CS2#
MM_CS3#
MM_RAS#
MM_CAS#
MM_WE#
Pin Name
BGA
W10
W12
W13
W19
W20
W18
W17
W16
W14 NORM3
W15 NORM3
W11
Ball
Y10
Y12
V12
Y13
Y14
Y20
V18
U18
V19
V20
T18
V17
Y18
Y17
Y16
V15
Y19
U20
U19
Y15
Y11
W9
W8
W7
W6
W5
W4
W1
W2
W3
Y9
V9
Y8
Y7
Y6
V6
Y5
Y4
V2
V3
Y1
Y2
Y3
U1
U2
U3
NORM3
NORM3
NORM3
NORM3
NORM3
STRG3
Type
Pad
Mode
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
SDRAM output clock at 2x or 3x TRI_CLKIN frequency. Two identical outputs are pro-
vided to reliably drive several small memory configurations without external glue.
A series terminating resistor close to PNX1300/01/02/11 is required to reduce ringing.
For driving a 50-ohm trace, a resistor of 27 to 33 ohm is recommended. It is recom-
mended against using higher impedance traces in the SDRAM signals.
Main memory address bus; used for row and column addresses
WARNING: MM_A[13:11] DO NOT CONNECT DIRECTLY TO SDRAM A[13:11] pins.
Refer to
32-bit data I/O bus.
The Main Memory Interface unit also supports a 16-bit I/O interface. Refer to
12, “SDRAM Memory System.”
Clock enable output to SDRAMs. Two identical outputs are provided in order to reli-
ably drive several small memory configurations without external glue.
Chip select for DRAM rank n; active low
In PNX1300/01/02/11 the chip selects pins may be used as address pins to support
the 256 Mbit SDRAM device organized in x16. Refer to
System.”
Row address strobe; active low
Column address strobe; active low
Write enable; active low
Main Memory Interface
Chapter 12, “SDRAM Memory System”
PRELIMINARY SPECIFICATION
Description
for accurate connection diagrams.
Chapter 12, “SDRAM Memory
Pin List
Chapter
1-3