PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 353

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
fmulflags
SYNTAX
FUNCTION
DESCRIPTION
rsrc1×rsrc2 and stores a bit vector representing the exception flags into rdest. The argument values are in IEEE
single-precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same
format as the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation.
Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted
before computing the product, and the IFZ bit in the result is set. If the product would be denormalized, the OFZ bit in
the result is set.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-55
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e–38)
r41 = 0x3f000000 (0.5),
r80 = 0x00800000 (1.17549435e–38)
r42 = 0x7f800000 (+INF),
r43 = 0x0 (0.0)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
r82 = 0x00c00000 (1.763241526e–38),
r83 = 0x8080000 (–1.175494351e–38)
r84 = 0x7f800000 (+INF),
r85 = 0xff800000 (–INF)
r70 = 0x7f7fffff (3.402823466e+38)
r80 = 0x00800000 (1.763241526e–38)
The
The
[ IF rguard ] fmulflags rsrc1 rsrc2 → rdest
if rguard then
fmulflags
rdest ← ieee_flags((float)rsrc1 × (float)rsrc2)
fmulflags
31
0
Initial Values
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation computes the IEEE exceptions that would result from computing the product
PRELIMINARY SPECIFICATION
fmulflags r60 r30 → r90
fmulflags r40 r60 → r95
IF r10 fmulflags r40 r80 → r100
IF r20 fmulflags r40 r80 → r105
fmulflags r41 r80 → r110
fmulflags r42 r43 → r106
fmulflags r40 r81 → r111
fmulflags r82 r83 → r112
fmulflags r84 r85 → r113
fmulflags r70 r70 → r120
fmulflags r80 r80 → r125
IEEE status flags from floating-point multiply
Operation
7
0
OFZ
6
IFZ
5
INV
4
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
fmul faddflags readpcsw
r90 ← 0
r95 ← 0
no change, since guard is false
r105 ← 0
r110 ← 0x46 (OFZ UNF INX)
r106 ← 0x10 (INV)
r111 ← 0x20 (IFZ)
r112 ← 0x06 (UNF INX)
r113 ← 0
r120 ← 0x0a (OVF INX)
r125 ← 0x06 (UNF INX)
OVF
3
Philips Semiconductors
UNF
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
ifmul
143
2, 3
No
—
2
3