PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 520

• Manufacturer Part Number: PNX1300EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1300EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
C-4
Figure C-3. Byte mask, planar YUV 4:2:0 and YUV 4:2:2 for ICP, VO or VI memory data in Little and Big En-
dian modes
Figure C-4. RBG-24+α data format for ICP in Little and Big Endian modes
Figure C-5. RBG-15+α data format for ICP in Little and Big Endian modes
Y pixel byte data
in memory
(same for U, V, B)
Pixel half-word data
in memory or PCI
Pixel word data
in memory or PCI
PRELIMINARY SPECIFICATION
31
31
31
A+3
Y3
A+3
G1B1
G3B3
Y7
B0
B1
A+3
Big Endian Mode
Big Endian Mode
P
n+1
αR1G’1
αR3G’3
A+2
Big Endian Mode
A+2
Y2
Y6
G0
G1
A+2
A+1
A+1
G0B0
G2B2
Y1
Y5
A+1
R0
R1
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy/PCI
and A+3 corresponds to byte-3 lane of SDRAM/Hwy/PCI
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy/PCI
and A+3 corresponds to byte-3 lane of SDRAM/Hwy/PCI
P
and A+3 corresponds to byte-3 lane of SDRAM/Hwy
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy
n
αR2G’2
αR0G’0
A+0
A+0
Y0
Y4
α0
α1
A+0
0
0
0
31
31
31
αR3G’3
αR1G’1
A+3
Y3
Y7
A+3
Little Endian Mode
α0
α1
A+3
Little Endian Mode
P
Little Endian Mode
n+1
A+2
A+2
Y2
Y6
G1B1
G3B3
A+2
R0
R1
Philips Semiconductors
A+1
αR2G’2
A+1
αR0G’0
Y1
Y5
A+1
G0
G1
P
n
A+0
A+0
Y0
Y4
G0B0
G2B2
A+0
B0
B1
0
0
0