PNX1300EH NXP Semiconductors, PNX1300EH Datasheet - Page 522
PNX1300EH
Manufacturer Part Number
PNX1300EH
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1300EH.pdf
(548 pages)
Specifications of PNX1300EH
Lead Free Status / RoHS Status
Not Compliant
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PNX1300/01/02/11 Data Book
C-6
Figure C-9. RGB8A and RGB8R data format for ICP in Little and Big Endian modes
Figure C-10. Half-word swap within a half-word (BSH)
Figure C-11. Packed RBG-24 data format for ICP in Little Endian mode only
RGB 8A or 8R
in Memory or PCI
(Same for U, V, B)
Pixel Word Data
in Memory or PCI
Before swap
After Swap
PRELIMINARY SPECIFICATION
31
A+3
P3
P7
Big Endian Mode
NOT SUPPORTED
Big Endian Mode
A+2
P2
P6
A+1
31
P1
P5
31
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCI
Note: A+0 corresponds to byte-zero lane of SDRAM/Hwy/PCI
and A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
and A+3 corresponds to byte-three lane of SDRAM/Hwy/PCI
04
05
A+0
P0
P4
05
04
0
31
06
07
31
A+3
P3
P7
A+3
R3
Little Endian Mode
G2
B1
Little Endian Mode
07
06
A+2
A+2
P2
P6
G3
R0
B2
Philips Semiconductors
0
0
A+1
A+1
P1
P5
B3
G0
R1
A+0
A+0
P0
P4
G1
R2
B0
0
0
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