MT46H64M16LFCK-75:A TR Micron Technology Inc, MT46H64M16LFCK-75:A TR Datasheet - Page 18
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MT46H64M16LFCK-75:A TR
Manufacturer Part Number
MT46H64M16LFCK-75:A TR
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H64M16LFCK-75A_TR.pdf
(96 pages)
Specifications of MT46H64M16LFCK-75:A TR
Organization
64Mx16
Density
1Gb
Address Bus
14b
Access Time (max)
6.5/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
105mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
Table 5: AC/DC Electrical Characteristics and Operating Conditions (Continued)
Notes 1–5 apply to all parameters/conditions in this table; V
Table 6: Capacitance (x16, x32)
Note 1 applies to all the parameters in this table
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
Parameter/Condition
Output leakage current
(DQ are disabled; 0V ≤ V
Operating temperature
Commercial
Industrial
Parameter
Input capacitance: CK, CK#
Notes:
OUT
≤ V
10. CK and CK# input slew rate must be ≥1 V/ns (2 V/ns if measured differentially).
11. V
12. The value of V
13. DQ and DM input slew rates must not deviate from DQS by more than 10%. 50ps must
1. All voltages referenced to V
2. All parameters assume proper device initialization.
3. Tests for AC timing, I
4. Outputs measured with equivalent load; transmission line delay is assumed to be very
5. Timing and I
6. Any positive glitch must be less than one-third of the clock cycle and not more than
7. V
8. To maintain a valid level, the transitioning edge of the input must:
9. V
DDQ
nominal supply voltage levels, but the related specifications and device operation are
guaranteed for the full voltage range specified.
small:
but input timing is still referenced to V
output timing reference voltage level is V
+200mV or 2.0V, whichever is less. Any negative glitch must be less than one-third of
the clock cycle and not exceed either –150mV or +1.6V, whichever is more positive.
8a. Sustain a constant slew rate from the current AC level through to the target AC lev-
el, V
8b. Reach at least the target AC level.
8c. After the AC target level is reached, continue to maintain at least the target DC lev-
el, V
be greater than one-third of the cycle rate. V
width ≤3ns and the pulse width cannot be greater than one-third of the cycle rate.
el on CK#.
variations in the DC level of the same.
be added to
4 V/ns, functionality is uncertain.
)
DD
IH
ID
overshoot: V
is the magnitude of the difference between the input level on CK and the input lev-
and V
IL(AC)
IL(DC)
I/O
or V
or V
DDQ
Full drive strength
DD
t
DS and
IH(AC)
IH(DC)
must track each other and V
IX
tests may use a V
IH,max
50
is expected to equal V
Symbol
.
.
I
T
T
DD
t
OZ
DH for each 100 mV/ns reduction in slew rate. If slew rate exceeds
A
A
= V
, and electrical AC and DC characteristics may be conducted at
Symbol
DD
DDQ
18
C
/V
SS
20pF
CK
DDQ
.
+ 1.0V for a pulse width ≤3ns and the pulse width cannot
IL
= 1.70–1.95V
-to-V
1Gb: x16, x32 Mobile LPDDR SDRAM
Min
I/O
–40
Micron Technology, Inc. reserves the right to change products or specifications without notice.
–5
0
DDQ
IH
DDQ
Half drive strength
Min
1.5
swing of up to 1.5V in the test environment,
DDQ
/2 of the transmitting device and must track
/2 (or to the crossing point for CK/CK#). The
DDQ
IL
/2.
50
must be less than or equal to V
undershoot: V
Max
Max
Electrical Specifications
+70
+85
3.0
5
10pF
© 2007 Micron Technology, Inc. All rights reserved.
IL,min
= –1.0V for a pulse
Unit
pF
Unit
μA
˚C
˚C
DD
Notes
Notes
.