MT46H64M16LFCK-75:A TR Micron Technology Inc, MT46H64M16LFCK-75:A TR Datasheet - Page 69
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MT46H64M16LFCK-75:A TR
Manufacturer Part Number
MT46H64M16LFCK-75:A TR
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H64M16LFCK-75A_TR.pdf
(96 pages)
Specifications of MT46H64M16LFCK-75:A TR
Organization
64Mx16
Density
1Gb
Address Bus
14b
Access Time (max)
6.5/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
105mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
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Figure 32: Data Input Timing
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
Notes:
Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as
shown in Figure 42 (page 78) and Figure 43 (page 79). Note that only the data-in
pairs that are registered prior to the
any subsequent data-in should be masked with DM, as shown in Figure 42 (page 78)
and Figure 43 (page 79). After the PRECHARGE command, a subsequent command to
the same bank cannot be issued until
DQS
DM
CK#
DQ
CK
1. WRITE command issued at T0.
2.
3.
4. For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 con-
5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 con-
4
5
t
t
trols DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
trols DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
t
WPRES
T0
t
1
DQSS
t DS
T1
D
b
IN
t
WPRE
t
DSH
t DH
69
T1n
2
t
Transitioning Data
t
DQSL
DSS
t
WR period are written to the internal array, and
3
t
T2
1Gb: x16, x32 Mobile LPDDR SDRAM
t
RP is met.
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
DQSH
DSH
T2n
2
t
t
WPST
DSS
3
T3
Don’t Care
© 2007 Micron Technology, Inc. All rights reserved.
WRITE Operation
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