MT46H64M16LFCK-75:A TR Micron Technology Inc, MT46H64M16LFCK-75:A TR Datasheet - Page 67
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT46H64M16LFCK-75:A TR
Manufacturer Part Number
MT46H64M16LFCK-75:A TR
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H64M16LFCK-75A_TR.pdf
(96 pages)
Specifications of MT46H64M16LFCK-75:A TR
Organization
64Mx16
Density
1Gb
Address Bus
14b
Access Time (max)
6.5/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
105mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
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Figure 31: Data Output Timing –
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
All DQ values, collectively
Command
DQS or LDQS/UDQS
CK#
CK
READ
T0
Notes:
3
2
1. Commands other than NOP can be valid during this cycle.
2. DQ transitioning after DQS transitions define
3. All DQ must transition by
4.
NOP
T1
t
AC is the DQ output window relative to CK and is the long-term component of DQ skew.
CL = 3
1
t
LZ
t
AC and
NOP
T2
t
t
RPRE
DQSCK
t
1
t
DQSCK
LZ
t
AC
T2n
4
T2
t
67
DQSQ after DQS transitions, regardless of
NOP
T3
1
T2n
1Gb: x16, x32 Mobile LPDDR SDRAM
T3n
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSCK
t
AC
T3
NOP
4
T4
t
1
DQSQ window.
T3n
T4n
T4
NOP
T5
1
© 2007 Micron Technology, Inc. All rights reserved.
T4n
T5n
READ Operation
t
AC.
T5
NOP
T6
1
Don’t Care
T5n
t
t
t
HZ
HZ
RPST
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