TSPC106AMGS66CG E2V, TSPC106AMGS66CG Datasheet
TSPC106AMGS66CG
Specifications of TSPC106AMGS66CG
Related parts for TSPC106AMGS66CG
TSPC106AMGS66CG Summary of contents
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Features Processor Bus Frequency MHz and 83.3 MHz • 64-bit Data Bus and 32-bit Address Bus • L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes • Provides Support for Either Asynchronous SRAM, Burst SRAM • or Pipelined ...
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Figure 1. TSPC106 Block Diagram Memory Interface Memory Target Functional Description TSPC106A 2 Power Management Error/Interrupt Control Master PCI Interface PCI Bus The TSPC106 provides a PowerPC the PowerPC microprocessor family and the PCI bus. CHRP is a set of ...
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The TSPC106 provides support for the following configurations of 60x processors and L2 cache: • four 60x processors with no L2 cache • A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal L2 ...
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Pin Description Figure 2. TSPC106 in 303-ball CBGA Package DL26 DL28 DL30 DH31 V DL24 DL27 DL29 DL31 MA1/ U SDBA0/ DL23 DL25 DL14 AR9 MA2/ T SDMA2/ WE DH0 DL15 AR10 MA3/ R SDMA3/ ...
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Figure 3. Pin Assignments Shading Ley NC No connect V SS Power Supply Ground Pinout Table 1. TSPC106 Pinout in 303-ball CBGA Package Signal Name 60x Processor Interface Signals A[0:31] AACK ARTRY BG0 BG1 (DIRTY_OUT) BG2 (TWE) BG3 (DCS) BR0 ...
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Table 1. TSPC106 Pinout in 303-ball CBGA Package (Continued) Signal Name Pin Number MCP J11 TA N1 TBST L4 TEA TSIZ[0:2] G3, G4, F3 TT[0:4] G1, H1, K1, L1 XATS (SDMA1 Cache ...
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Table 1. TSPC106 Pinout in 303-ball CBGA Package (Continued) Signal Name PPEN RAS/CS[0:7] RCS0 RCS1 RTC SDRAS (PIRQ) WE PCI Interface Signals (2) (2) AD[31:0] (2) C/BE[3:0] DEVSEL FLSHREQ FRAME GNT IRDY ISA_MASTER (BERR) LOCK MEMACK PAR PERR PIRQ (SDRAS) ...
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Table 1. TSPC106 Pinout in 303-ball CBGA Package (Continued) Signal Name Pin Number TCK F13 TDI B13 TDO E12 TMS D14 TRST H13 Power and Ground Signals (3) LSSD_MODE G11 E10, E6, F11, F5, F7, G10, G12, ...
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Figure 4. Symbol PCI Interface Memory Interface Interrupt, Clock and Power Management Signals Configuration Note: Some signals have dual functions and are shown more than once in this figure. 2102C–HIREL–01/05 AD[31:0] 32 C/BE[3:0] 4 PAR 1 TRDY 1 IRDY 1 ...
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Processor Interface Signals Table 2. 60x Processor Interface Signals Signal Signal Name A[0:31] Address bus Address AACK acknowledge ARTRY Address retry BG0 Bus grant 0 BR0 Bus request 0 CI Cache inhibit DBG0 Data bus grant 0 Local bus ...
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Table 2. 60x Processor Interface Signals (Continued) Signal Signal Name DH[0:31], Data bus DL[0:31] GBL Global Local bus slave LBCLAIM cycle claim MCP Machine check Transfer TA acknowledge TBST Transfer burst Transfer error TEA acknowledge TS Transfer start 2102C–HIREL–01/05 Number ...
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Table 2. 60x Processor Interface Signals (Continued) Signal Signal Name TSIZ[0:2] Transfer size TT[0:4] Transfer type WT Write-through Extended address XATS transfer start L2 Cache/Multiple Processor Interface Signals Internal L2 Controller Signals Table 3. Internal L2 Controller Signals Signal Signal ...
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Table 3. Internal L2 Controller Signals (Continued) Signal Signal Name DOE Data RAM output DBGL2 enable DWE[0:2] Data RAM write DBG2 enable DBG3 Hit HIT TOE Tag output enable DBG1 TV Tag valid BR2 TWE Tag write enable BG2 External ...
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Multiple Processor Signals Table 5. Multiple Processor Signals Signal Signal Name BG1 Bus grant 1 DIRTY_OUT BG2 Bus grant 2 TWE BG3 Bus grant 3 DCS BR1 Bus request 1 DIRTY_IN BR2 Bus request 2 TV BR3 Bus request 3 ...
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Memory Interface Signals Table 6. Memory Interface Signals Signal Signal Name AR0 ROM address 0 MA0 AR[1:8] ROM address PAR[0:7] AR[9:20] ROM address MA[1:12 BCTL[0:1] Buffer control Column address CAS[0:7] strobe ...
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PCI Interface Signals Table 7. PCI Interface Signals Signal Signal Name AD[31:0] Address/data Command/byte C/BE[3:0] enable DEVSEL Device select FLSHREQ Flush request FRAME Frame GNT PCI bus grant IRDY Initializer ready ISA_ ISA master MASTER LOCK Lock Memory MEMACK acknowledge ...
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Table 7. PCI Interface Signals Signal Signal Name PAR Parity PERR Parity error Modified memory PIRQ interrupt request REQ PCI bus request SERR System error STOP Stop TRDY Target ready 2102C–HIREL–01/05 Number of Pins I/O Signal Description Asserted indicates odd ...
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Interrupt, Clock and Power Management Signals The TSPC106 coordinates interrupt, clocking, and power management signals across the memory bus, the PCI bus and the 60x processor bus. Table 8. Interrupt, Clock and Power Management Signals Signal Signal Name CKO Test ...
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Configuration Signals Table 10. Configuration Signals Signal Number of Pins (1) DBG0 1 (1) FOE 1 (2) PLL[0:3] 4 (1) RCS0 1 Notes: 1. The TSPC106 samples these signals during a power-on reset or hard reset operation to determine the ...
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Detailed Specifications Scope Applicable Documents Requirements General Design and Construction Absolute Maximum Ratings Thermal Characteristics TSPC106A 20 This drawing describes the specific requirements of the TSPC106 in compliance with MIL-STD-883 class B or manufacturer’s standard screening. Documents applicable to the ...
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Figure 5. Exploded Cross-section CI_CGA Package Internal Package Conduction Resistance Figure 6. C4/CBGA Package Mounted on a Printed Circuit Board External Resistance Internal Resistance External Resistance Note: Internal package resistance differs from external package resistance. 2102C–HIREL–01/05 After the C4 solder ...
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Power Consumption Full-power Mode Doze Mode Nap Mode Sleep Mode Suspend Mode TSPC106A 22 The TSPC106 provides hardware support for four levels of power reduction – the doze, nap and sleep modes are invoked by register programming and the suspend ...
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Power Dissipation Marking 2102C–HIREL–01/05 Table 13 provides figures on power consumption for the TSPC106. Table 13. Power Consumption Mode SYSCLK/Core33/66 MHz Full-on Mode Typical 1.2 Maximum 1.4 Doze Mode Typical 1.0 Maximum 1.2 Nap Mode Typical 1.0 Maximum 1.2 Sleep ...
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Electrical Characteristics Table 14. Recommended Operating Conditions Characteristic Symbol Supply voltage V DD PLL supply voltage AV DD Input voltage V in Die junction T j temperature General Requirements Table 15. Clock DC Timing Specifications (V Symbol Characteristic V Input ...
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Dynamic Characteristics Clock AC Specifications Table 16. Clock AC Timing Specifications (V Ref Characteristic 60x processor bus (core) frequency (1) VCO frequency (1) SYSCLK frequency 1 SYSCLK cycle time 2, 3 SYSCLK rise and fall time 4 SYSCLK duty cycle ...
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Input AC Specifications Table 17. Input AC Timing Specifications (V Ref Characteristic Group I input signals valid to SYSCLK (input 10a ( setup) Group II input signals valid to SYSCLK (input 10a ( setup) Group III ...
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Figure 8. Input Timing Diagram SYSCLK 10a 10b All Inputs Note Midpoint Voltage (1.4V) Figure 9. Mode Select Input Timing Diagram HRST MODE Pins Note Midpoint Voltage (1.4V) VM 11a VM 10c 11c 27 ...
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Output AC Specifications Table 18 provides the output AC timing specifications as shown in Figure 10. Table 18. Output AC Timing Specifications (V Ref Characteristic SYSCLK to output driven (output enable 12 (9) time) SYSCLK to output valid (for TS ...
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Figure 10. Output Timing Diagram VM SYSCLK 12 All Outputs (except TS and ARTRY ARTRY Note Midpoint Voltage (1.4V) Table 19. JTAG AC Timing Specifications (Independent of SYSCLK) (V -55°C ≤ T ≤ 125°C) j Ref ...
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Figure 11. JTAG Clock Input Timing Diagram TCK 3 Figure 12. TRST Timing Diagram TCK TRST Figure 13. Boundary-scan Timing Diagram TCK Data Inputs Data Outputs Data Outputs Data Outputs TSPC106A ...
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Figure 14. Test Access Port Timing Diagram TCK TDI, TMS TDO TDO TDO Architectural Overview 60x Processor Interface Secondary (L2) Cache/Multiple Processor Interface 2102C–HIREL–01/ The TSPC106 supports a programmable interface to a variety of PowerPC microproces- sors ...
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Memory Interface TSPC106A 32 When more than one 60x processor is used, nine signals of the L2 interface change their functions (to BR[1:3], BG[1:3] and DBG[1:3]) to allow for arbitration between the 60x processors. The 60x processors share all 60x ...
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PCI Interface System Design Information PLL Configuration 2102C–HIREL–01/05 The TSPC106’s PCI interface is compliant with the PCI Local Bus Specification, Revi- sion 2.1, and follows the guidelines in the PCI System Design Guide, Revision 1.0 for host bridge architecture. The ...
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Table 20. Core/VCO Frequencies and PLL Settings Core/SYSCL PLL[0:3](1) Ratio 0010 1:1 0101 2:1 (2) 0110 5:2 (2) 0111 5:2 1000 3:1 1001 3:1 0011 PLL Bypass 1111 Clock off Notes: 1. PLL[0:3] settings not listed are reserved. Some PLL ...
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Decoupling Recommendations Connection Recommendations Pull-up Resistor Recommendations 2102C–HIREL–01/05 Due to the TSPC106's large address and data buses, and high operating frequencies, the TSPC106 can generate transient power surges and high frequency noise in its power supply, especially while driving large ...
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Table 21. Pull-up/Pull-down Recommendations Signal Type 60x bus control 60x bus address/transfer attributes Cache control PCI bus control JTAG Factory test Preparation for Delivery Packaging Certificate of Compliance Handling TSPC106A 36 Signals BRn, TS, XATS, AACK, ARTRY, TA A[0:31], TT[0:4], ...
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Package Mechanical Data CBGA Package Parameters Table 22. CBGA Package Parameters Parameter Min Package outline Interconnects 303 ( ball array minus one) Pitch 1.27 mm Solder attach 63/37 Sn/Pb Solder balls 10/90 Sn/Pb, ...
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CI_CGA Package Parameters Table 23. CI-CGA Package Parameters Parameter Min Package outline Interconnects 303 ( ball array minus one) Pitch 1.27 mm Solder attach 63/37 Sn/Pb Solder balls 10/90 Sn/Pb, 0.89 mm diameter ...
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Ordering Information Definitions Datasheet Status Objective specification Target specification Preliminary specification α site Preliminary specification β site Product specification Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stresses above one or more ...
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Life Support Applications Document Revision History Table 24. Revision History Revision Number Date 2102C 11/2004 TSPC106A 40 These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...