TSPC106AMGS66CG E2V, TSPC106AMGS66CG Datasheet - Page 15

• Manufacturer Part Number: TSPC106AMGS66CG
• Manufacturer: E2V

Specifications of TSPC106AMGS66CG

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

Memory Interface
Signals
Table 6. Memory Interface Signals
2102C–HIREL–01/05
Signal
AR0
MA0
AR[1:8]
PAR[0:7]
AR[9:20]
MA[1:12]
BCTL[0:1]
CAS[0:7]
FOE
MA0
MA[1:12]
AR0
AR[9:20]
MDLE
PAR[0:7]
AR[1:8]
PPEN
RAS[0:7]
RCS0
RCS1
RTC
WE
Signal Name
ROM address 0
ROM address 1 - 8
ROM address
9 - 20
Buffer control 0 - 1
Column address
strobe 0 - 7
Flash output
enable
Memory address
0 - 12
Memory data latch
enable
Data parity/ECC
Parity path read
enable
Row address
strobe 0 - 7
ROM/Flash bank 0
select
ROM/Flash bank 1
select
Real-time clock
Write enable
Number of
Table 6 lists the memory interface signals and provides a brief description of their func-
tions. The memory interface supports either standard DRAMs or EDO DRAMs, and
either standard ROMs or Flash ROMs. Some of the memory interface signals perform
different functions depending on the RAM and ROM configurations.
Pins
12
13
8
8
2
8
1
1
8
1
8
1
1
1
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
Enables Flash output for the current read access.
Signal Description
Represents address bit 0 of the 8-bit ROM/Flash. Note that AR0 is only
supported for ROM bank 0 when configured for an 8-bit ROM/Flash data
bus width. The extra address bit allows for up to 2 Mbytes of ROM when
using the 8-bit wide data path. Bits 1 - 8 of the ROM address are provided
by AR[1:8] and bits 9 - 20 of the ROM address are provided by AR[9:20].
Represents bits 1 - 8 of the ROM/Flash address. The other ROM address
bits are provided by AR0 and AR[9:20].
Represents bits 9 - 20 of the ROM/Flash address (the 12 lowest order bits,
with AR20 as the least significant bit (lsb)). Bits 0 - 8 of the ROM address
are provided by AR0 and AR[1:8].
Used to control external data bus buffers (directional control and high-
impedance state) between the 60x bus and memory. Note that external
data buffers may be optional for lightly loaded data buses, but buffers are
required whenever an L2 cache and ROM/Flash (on the 60x/memory bus)
are both in the system or when ECC is used.
Indicates a memory column address is valid and selects one of the
columns in the row. CAS0 connects to the most significant byte select.
CAS7 connects to the least significant byte select.
Represents the row/column multiplexed physical address for DRAMs or
EDOs (MA0 is the most significant address bit; MA12 is the least significant
address bit). Note that MA0 also functions as the ROM address signal AR0
and MA[1:12] function as the ROM address signals AR[9:20].
Enables the external, latched data buffer for read operations, if such a
buffer is used in the system.
Represents the byte parity or ECC being written to memory (PAR0 is the
most significant bit).
Represents the byte parity or ECC being read from memory (PAR0 is the
most significant bit).
Enables external parity/ECC bus buffer or latch for memory read
operations.
Indicates a memory row address is valid and selects one of the rows in the
bank.
Selects ROM/Flash bank 0 for a read access or Flash bank 0 for a read or
write access.
Selects ROM/Flash bank 1 for a read access or Flash bank 1 for a read or
write access.
External clock source for the memory refresh logic when the TSPC106 is in
the suspend power-saving mode.
Enables writing to DRAM, EDO or Flash.
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