TSPC106AMGS66CG E2V, TSPC106AMGS66CG Datasheet - Page 28

• Manufacturer Part Number: TSPC106AMGS66CG
• Manufacturer: E2V

Specifications of TSPC106AMGS66CG

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

Output AC Specifications
Table 18 provides the output AC timing specifications as shown in Figure 10.
Table 18. Output AC Timing Specifications (V
Notes:
28
Ref
13a
13b
14a
14b
15a
15b
12
18
19
21
1. Processor and memory interface signals are specified from the rising edge of the 60x bus clock.
2. Output specifications are measured from 1.4V on the rising edge of SYSCLK to the TTL level (0.8V or 2.0V) of the signal in
3. The maximum timing specification assumes C
4. The shared outputs TS and ARTRY require pull-up resistors to hold them negated when there is no bus master driving them.
5. When the TSPC106 is configured for asynchronous L2 cache SRAMs, the DWE[0:2] signals have a maximum SYSCLK to
6. PCI 3.3V signaling environment signals are measured from 1.65V (V
7. The minimum timing specification assumes C
8. t
9. These values are guaranteed by design and are not tested.
10. PCI devices which require more than the PCI-specified hold time of T
TSPC106A
question. Both input and output timings are measured at the pin.
output valid time of (0.5 x t
V
bers given in the table must be multiplied by the period of SYSCLK to compute the actual duration in nanoseconds of the
parameter in question.
PCI-specified allowance of 2 ns may not work with the TSPC106. For workarounds, see Freescale application note “Design-
ing PCI 2.1-compliant MPC106 Systems” (order number AN1727/D).
Characteristic
SYSCLK to output driven (output enable
time)
SYSCLK to output valid (for TS and
ARTRY)
signals except TS, ARTRY, RAS[0:7] and
CAS[0:7]) and DWE[0:2]
SYSCLK to output valid (for RAS[0:7] and
CAS[0:7])
SYSCLK to output valid
(for PCI signals)
SYSCLK to output invalid for all non-PCI
signals (output hold)
SYSCLK to output valid for PCI signals
(output hold)
SYSCLK to ARTRY high impedance
before precharge (output hold)
SYSCLK to ARTRY precharge enable
SYSCLK to ARTRY high impedance after
precharge
SYSCLK
SYSCLK to output valid (for all non-PCI
OL
= 0.3V.
(9)
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as t
(1, 2, 3, 4)
(1, 2, 3)
(8, 9)
(7)
(3, 6)
(7, 10)
(1, 2, 3, 5)
PROC
(9)
) + 8.0 ns (where t
(8, 9)
DD
= 3.3V ± 5% dc, GND = 0V dc, C
L
(0.4 x t
L
= 50 pF.
= 50 pF.
PROC
+ 2.0
Min
2.0
1.0
1.0
SYSCLK
is the 60x bus clock cycle time).
66 MHz
)
(1.5 x t
+ 8.0
Max
11.0
7.0
7.0
7.0
8.0
DD
SYSCLK
H
= 0 ns or systems where clock skew approaches the
÷ 2) on the rising edge of SYSCLK to V
)
L
(0.4 x t
= 50 pF, -55°C ≤ T
+ 2.0
Min
2.0
1.0
1.0
SYSCLK
83.3 MHz
)
(1.5 x t
+ 8.0
Max
11.0
j
6.0
6.0
6.0
8.0
≤ 125°C)
SYSCLK
2102C–HIREL–01/05
SYSCLK
)
OH
, the num-
= 3.0V or
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns