TSPC106AMGS66CG E2V, TSPC106AMGS66CG Datasheet - Page 34

• Manufacturer Part Number: TSPC106AMGS66CG
• Manufacturer: E2V

Specifications of TSPC106AMGS66CG

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

Table 20. Core/VCO Frequencies and PLL Settings
Notes:
PLL Power Supply
Filtering
34
PLL[0:3](1)
0010
0101
0110
0111
1000
1001
0011
1111
1. PLL[0:3] settings not listed are reserved. Some PLL configurations may select bus, CPU or VCO frequencies which are not
2. 5:2 clock modes are only supported by TSPC106 Rev 4.0; earlier revisions do not support 5:2 clock modes. The 5:2 modes
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal circuitry directly, the PLL is disabled and the
4. In clock-off mode, no clocking occurs inside the TSPC106 regardless of the SYSCLK input.
5. PLL[0:3] = 0010 (1:1 Core/SYSCLK Ratio; X8 VCO Multiplier) exists on the chip but will fail to lock 50% of the time. There-
TSPC106A
useful, not supported or not tested. See “Input AC Specifications” on page 26 for valid SYSCLK and VCO frequencies.
require a 60x bus clock applied to the 60x clock phase (LBCLAIM) configuration input signal during power-on reset, hard
reset and coming out of sleep and suspend power saving modes.
core/SYSCLK ratio is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
fore this configuration should not be used and 1:1 modes between 16 and 25 MHz are not supported.
Core/SYSCL
Ratio
5:2
5:2
1:1
2:1
3:1
3:1
(2)
(2)
PLL Bypass
Clock off
The AV
phase-locked loop. To ensure stability of the internal clock, the power supplied to the
AV
The circuit should be placed as close as possible to the AV
as much noise as possible.
Figure 15. PLL Power Supply Filter Circuit
VCO Multiplier
DD
(4)
(3)
input signal should be filtered using a circuit similar to the one shown in Figure 15.
DD
x8
x4
x2
x4
x2
x4
power signal is provided on the 106 to provide power to the clock generation
V DD
(3.3V)
41.6 (166)
16.6 MHz
PCI Bus
10Ω
Core Frequency (VCO Frequency) in MHz
10 µF
SYSCLK clocks core circuitry directly
1 x core/SYSCLK ratio implied
PCI Bus
40 (160)
50 (200)
60 (240)
20 MHz
No core clocking occurs
GND
PLL off
PLL off
0.1 µF
62,5 (250)
PCI Bus
50 (200)
75 (150)
75 (300)
25 MHz
DD
pin to ensure it filters out
AV DD
2102C–HIREL–01/05
33.3 (266)
66.6 (266)
83.3 (166)
83,3 (333)
33.3 MHz
PCI Bus