TSPC106AMGS66CG E2V, TSPC106AMGS66CG Datasheet - Page 11

• Manufacturer Part Number: TSPC106AMGS66CG
• Manufacturer: E2V

Specifications of TSPC106AMGS66CG

• Operating Temperature Classification: Military
• Operating Temperature (max): 125C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

Table 2. 60x Processor Interface Signals (Continued)
2102C–HIREL–01/05
Signal
DH[0:31],
DL[0:31]
GBL
LBCLAIM
MCP
TA
TBST
TEA
TS
Signal Name
Data bus
Global
Local bus slave
cycle claim
Machine check
Transfer
acknowledge
Transfer burst
Transfer error
acknowledge
Transfer start
Number of
Pins
64
1
1
1
1
1
1
1
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
Signal Description
The data bus is comprised of two halves - data bus high (DH[0:31])
and data bus low (DL[0:31]). The data bus has the following byte lane
assignments:
Represents the value of data being driven by the TSPC106.
Represents the state of data being driven by a 60x processor, the local
bus slave, the L2 cache or the memory subsystem.
Indicates that an access is global and hardware needs to enforce
coherency.
Indicates that the local bus slave claims the transaction and is
responsible for driving TA during the data tenure.
Indicates that the TSPC106 detected a catastrophic error and the 60x
processor should initiate a machine check exception.
Indicates that the data has been latched for a write operation or that
the data is valid for a read operation, thus terminating the current data
beat. If it is the last (or only) data beat, this also terminates the data
tenure.
Indicates that the external L2 cache or local bus slave has latched data
for a write operation or is indicating the data is valid for a read
operation. If it is the last (or only) data beat, then the data tenure is
terminated.
Indicates that a burst transfer is in progress.
Indicates that a burst transfer is in progress.
Indicates that a bus error has occurred. Assertion of TEA terminates
the transaction in progress. An unsupported memory transaction, such
as a direct-store access or a graphics read or write, causes the
assertion of TEA (provided TEA is enabled).
Indicates that the TSPC106 has started a bus transaction and that the
address and transfer attribute signals are valid. Note that the
TSPC106 only initiates a transaction to broadcast the address of a PCI
access to memory for snooping purposes.
Indicates that a 60x bus master has begun a transaction and that the
address and transfer attribute signals are valid.
Data Byte
DH[16:23]
DH[24:31]
DL[16:23]
DL[24:31]
DH[8:15]
DL[8:15]
DH[0:7]
DL[0:7]
Byte Lane
0
1
2
3
4
5
6
7
11